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Conferences, Lectures, & Seminars
Events for April
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FPGAs: Democratizing System-on-chip Design, Re-defining Digital Systems Design
Tue, Apr 04, 2006 @ 02:00 PM - 03:20 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
CENG SEMINAR SERIES"FPGAs: Democratizing system-on-chip design, re-defining digital systems design"Prof. Patrick LysaghtSenior DirectorXilinx Research LabAbstract:FPGAs have established themselves as the third programmable platform after CPUs and DSPs. Originally, they were perceived as low capacity, "glue logic" devices especially well suited for prototyping and low-volume applications. However as FPGA capacities and capabilities have expanded, they are now the preferred platform for most companies who are embarking on system-on-chip (SoC) design. This talk begins with a concise introduction to the capabilities of modern FPGAs and the dynamics of the new industry that they have created. This is followed by an examination of some new directions in research into dynamic reconfiguration, the unique capability of certain FPGA architectures to be partially reconfigured while operational. The representation of FPGA configuration information within the context of a host computer's virtual file system will be introduced and the capabilities and potential of this new metaphor will be discussed.Bio:Patrick Lysaght is a Senior Director in Xilinx Research Labs, whose research interests include reconfigurable computing (especially dynamically reconfigurable systems), embedded systems, system-level modeling and emerging design technologies for FPGAs. Patrick also leads Xilinx's University Program worldwide.Before joining Xilinx, Patrick was a senior lecturer at the University of Strathclyde (Glasgow) and at the Institute for System Level Integration (Livingston, Scotland). He started his career in research and development with Hewlett Packard (Edinburgh) and held a number of technical and marketing positions before joining academia. Patrick holds a BSc (Electronic Systems) from the University of Limerick, Ireland and an MSc degree (Digital Techniques) from Heriot-Watt University in Edinburgh, Scotland. He has co-authored more than forty technical papers and co-edited two books on programmable logic. He is chairman of the steering committee for FPL, the world's largest conference dedicated to field programmable logic.Host: Prof. Viktor Prasanna, Ext. 04483
Location: Olin Hall of Engineering (OHE) - -136
Audiences: Everyone Is Invited
Contact: Rosine Sarafian
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor. -
ELECTRICAL ENGINEERING-DISTINGUISHED LECTURER SERIES
Thu, Apr 06, 2006 @ 02:00 PM - 03:00 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
"Design in the Nano-Meter Regime: From Devices to System Architecture"Prof. Kaushik RoyRoscoe H. George Professor of ECECo-Director, Center for Wireless Systems & ApplicationsPurdue UniversityAbstract:Scaling of technology over the last few decades has produced an exponential growth in computing power of integrated circuits and an unprecedented number of transistors integrated into a single. However, scaling is facing several problems – severe short channel effects, exponential increase in leakage current, increased process parameter variations, and new reliability concerns. Hence, reliable, low-power designs require a shift in design paradigm. We believe that /device aware circuit and architecture design/ along with statistical design techniques can provide large improvement in power dissipation while providing the required reliability and yield. In this talk I will present device aware CMOS design to address power and reliability problems in scaled technologies for different application domains – high-performance with power as constraint and ultra-low power with reasonable performance.Bio:Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor and holds the Roscoe H. George Professor of Electrical & Computer Engineering. His research interests include VLSI design/CAD for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. Dr. Roy has published more than 350 papers in refereed journals and conferences, holds 8 patents, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim). Host: Prof. Massoud Pedram, ext. 04458 http://viterbi.usc.edu/calendar/
Location: Ethel Percy Andrus Gerontology Center (GER) - ontology Auditorium
Audiences: Everyone Is Invited
Contact: Rosine Sarafian
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor. -
COMPUTER ENGINEERING SEMINAR SERIES
Thu, Apr 06, 2006 @ 02:00 PM - 03:20 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
CENG SEMINAR SERIES"Optimized Compiler Generated Code Accelerators For FPGAs "Prof. Walid NajjarComputer Science & EngineeringUniversity of California, RiversideABSTRACT:Using FPGA devices to accelerate codes might have seemed an esoteric idea a few years ago. It is quickly moving into the mainstream not only for embedded but also supercomputer applications. Speedups ranging from 10x to 1000x have commonly been reported. FPGAs are commonly programmed using hardware description languages (HDL). HDLs are behavioral in nature and not easily amenable to high-level compiler transformations. In this paper we describe ROCCC (Riverside Optimizing Configurable Computing Compiler) a C to VHDL compiler that targets the automatic generation of FPGA-based accelerators. ROCCC optimizes and parallelizes the most frequently executed kernel loops in applications such as multimedia and scientific computing. Its objectives are to (1) bridge the performance gap between compiled and hand-written code and (2) apply extensive compile-time transformations on multi-dimensional arrays and non-trivial loop nests. Such transformations would be too complex for a human programmer to handle in a reasonable time. The objectives of the ROCCC optimizations are: (1) Maximize the parallelism in the circuit as well as the clock rate at which it operates. (2) Minimize the number of off-chip memory accesses as well as the area of the circuit. The main challenge that faces HLL to HDL translation is the paradigm shift from the stored program model to a value-based, data-driven execution – from temporal to a spatial execution. The task of an FPGA compiler is to generate both the data path and the sequence of operations (control flow) on that data path. The lack of architectural structure on the FPGA presents a number of opportunities for the compiler: (1) The parallelism is very high and limited only by the size of the FPGA or the bandwidth in or out of it. (2) On-chip storage can be configured at will. (3) Circuit customization allows the compiler to reduce the circuit size as well as the clock duration. We use dynamic programming applications, for DNA and protein string matching, to demonstrate the potentials of ROCCC. A relatively small C code that is mapped to the FPGA available on the Cray XD1 can achieve 1 to 100 Giga cell update per second. This translates to a two to four orders of magnitude speedup compared to a 2 GHz CPU with an ideal cache and no pipeline stalls.BIO:Walid A. Najjar is a Professor in the Department of Computer Science and Engineering at the University of California Riverside. He received a B.E. in Electrical Engineering from the American University of Beirut in 1979 and the M.S. and Ph.D. in Computer Engineering from the University of Southern California in 1985 and 1988 respectively. He was on the faculty of the Department of Computer Science at Colorado State University (1989 to 2000), before that he was with the USC-Information Sciences Institute. His research is in computer architecture, reconfigurable and embedded systems and compiler optimizations and has been supported by NSF, DARPA and various companies. He has served on the program committees for a number of leading conferences in this area including CASES, ISSS-CODES, DATE, HPCA, and MICRO.Host: Prof. Viktor Prasanna, x04483
Location: Olin Hall of Engineering (OHE) - -136
Audiences: Everyone Is Invited
Contact: Rosine Sarafian
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor. -
Information Theory and Probability Estimation: From Shannon to Shakespeare via...
Fri, Apr 07, 2006 @ 11:00 AM - 12:00 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Title: "Information Theory and Probability Estimation: From Shannon to Shakespeare via Laplace, Good, Turing, Hardy, Ramanujan, and Fisher"Speaker: Prof. Alon Orlitsky, UCSDAbstract: Standard information-theoretic results show that data over small, typically binary, alphabets can be compressed to Shannon's entropy limit. Yet most practical sources, such as text, audio, or video, have essentially infinite support. Compressing such sources requires estimating probabilities of unlikely, even unseen, events, a problem considered by Laplace. Of existing estimators, an ingenious if cryptic one derived by Good and Turing while deciphering the Enigma code works best yet not optimally. Hardy and Ramanujan's celebrated results on the number of integer partitions yield an asymptotically optimal estimator that compresses arbitrary-alphabet data patterns to their entropy. The same approach generalizes Fisher's seminal work estimating the number of butterfly species and its extension authenticating a poem purportedly written by The Bard. The talk covers these topics and is self-contained.Joint work with Prasad Santhanam, Krishna Viswanathan, and Junan ZhangBio: Alon Orlitsky received B.Sc. degrees in Mathematics and Electrical Engineering from Ben Gurion University in 1980 and 1981, and M.Sc. and Ph.D. degrees in Electrical Engineering from Stanford University in 1982 and 1986. From 1986 to 1996 he was with the Communications Analysis Research Department of Bell Laboratories. He spent the following year as a quantitative analyst at D.E. Shaw and Company, an investment firm in New York city. In 1997 he joined the University of California, San Diego, where he is currently a professor of Electrical and Computer Engineering and of Computer Science and Engineering. Alon's research concerns information theory, learning, and speech recognition. He is a recipient of the 1981 ITT International Fellowship and of the 1992 IEEE W.R.G. Baker Paper Award.Host: Professor Urbashi Mitra, ubli@usc.edu
Location: Hughes Aircraft Electrical Engineering Center (EEB) - -248
Audiences: Everyone Is Invited
Contact: Mayumi Thrasher
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor. -
Eigenvalues and Singular Values of Random Matrices: Theory and Applications
Fri, Apr 14, 2006 @ 11:00 AM - 12:00 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Communication Sciences Institute Seminar: Eigenvalues and Singular Values of Random Matrices: Theory and ApplicationsAntonia Tulino (University of Naples)Abstract:
Of late, random matrices have attracted great interest in the engineering community because of their applications to the communications and information theory on the fundamental limits of wireless communication noisy vector channels. The purpose of this talk is to illustrate this synergy between random matrix theory and information theory through several classes of channels that arise in wireless communications. These channels are characterized by random matrices that admit various statistical descriptions depending on the actual application. Motivated by the intuition drawn from various applications in communications, the _ and Shannon transforms turn out to be quite helpful at clarifying the exposition as well as the statement of many results. In this talk we revisit in terms of _- and Shannon-transform some of the main results in random matrix theory from the work of Mar_enko-Pastur in 1967 to the most recent asymptotic results in the contest of free probability theory and we give an extended summary of their main recent applications to wireless communication problems.In addition, recent results on the speed of convergence to the asymptotic limits are visited and used
to evaluate the probability density function of the mutual informationThroughout the talk, we apply the various findings to the fundamental limits of wireless communication with focus on several classes of vector channels that arise in wireless communications: • Code-division multiple-access (CDMA), with and without fading (both frequency-flat and frequency-selective) and with single and multiple receive antennas. • Multi-carrier code-division multiple access (MC-CDMA), which is the time-frequency dual of CDMA • Channels with multiple receive and transmit antennas, incorporating features such as antenna correlation, polarization, and line-of-sight components.For each of these channels, we analyze two performance measures of engineering interest: the average mutual information (highest data rate that can be conveyed reliably per unit bandwidth) and minimum mean-square error (smallest mean-square error that can be incurred estimating the channel input based on its noisy received observations), which are determined by the distribution of the singular values of the channel matrix.Bio:
Antonia Maria Tulino was born in Napoli, Italy, on September 12, 1971. She received the Dr. Engr. degree (summa cum laude) from the Università degli Studi di Napoli Federico II, Napoli, Italy, in 1995 and the Ph.D. degree in electronic engineering from the Seconda Università degli Studi di Napoli, Napoli, Italy, in 1999. In 1999, she was a Research Scientist at the Center for Wireless Communications (CWC), Oulu, Finland. From January 2000 to February 2001, she was a post-doctoral visitor with Princeton University, Princeton, NJ. From February 2001 to November to 2002, she was Assistant Professor with the Dipartmento di Ingegneria delle Telecomunicazioni, Università degli Studi del Sannio, Benevento, Italy. From Novembre to 2002 she has been Associate Professor with the Dipartmento di Ingegneria Elettronica e delle Telecomunicazioni, Università degli Studi di Napoli "Federico II", Napoli, Italy. She is periodically appointed as visiting research staff member at the Department of Electrical Engineering, Princeton University. Her current research interests are in the area of statistical signal processing, information theory, random matrix theory.
Location: Hughes Aircraft Electrical Engineering Center (EEB) - 248
Audiences: Everyone Is Invited
Contact: michael neely
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor. -
**Seminar Cancelled -- Will be rescheduled at a later date**
Tue, Apr 18, 2006
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
"Systematic with Serially Concatenated Parity Codes"Speaker: Prof. Keith Chugg
Location: Hughes Aircraft Electrical Engineering Center (EEB) - -248
Audiences: Everyone Is Invited
Contact: Mayumi Thrasher
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor. -
Cooperation in Wireless Networks: Node Assignment Strategies
Wed, Apr 19, 2006 @ 10:00 AM - 11:00 AM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Speaker: Prof. Aria Nosratinia, University of Texas, DallasAbstract: I will discuss cooperative wireless networks, in particular the non-altruistic variety where there are no pure relays and all nodes that are "on" have data of their own to transmit. In this context, a coded cooperation framework will be presented, where cooperation is achieved in the context of channel coding. Then we will proceed to discuss node assignment for cooperation. In general, not all nodes in a wireless network may wish to be involved in every transmission. Therefore, in a multi-node cooperation protocol, one needs strategies of grouping the nodes. Such strategies are examined under two types of constraints: distributed control and centralized control. We shall see that there exist simple distributed strategies that guarantee full diversity (in the number of decoding attempts) over the network. Since the distributed strategies already achieve full diversity, centralized control does not provide any additional diversity gain, however, based on various amounts of channel state information being available to the central controller, significant gains are still possible over and above distributed control. These gains are characterized under a variety of conditions.Bio: Aria Nosratinia is associate professor of electrical engineering at the University of Texas, Dallas (UTD). Currently he is spending a sabbatical leave at UCLA. Aria received his Ph.D. in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He has been a visiting scholar with Princeton University, Princeton, New Jersey and a visiting professor and faculty fellow at Rice University, Houston, Texas. His interests lie in the broad area of information theory, coding and signal processing, in particular various problems related to wireless networks and transmission of multimedia data over such networks. He received the National Science Foundation career award in January 2000. He serves as associate editor for the IEEE Transactions on Image Processing and IEEE Wireless Communications.Host: Professor Giuseppe Caire, caire@usc.edu, x.04683
Location: Hughes Aircraft Electrical Engineering Center (EEB) - -248
Audiences: Everyone Is Invited
Contact: Mayumi Thrasher
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor. -
THE MECHANISM OF THOUGHT: CONFABULATION
Wed, Apr 26, 2006 @ 02:30 PM - 04:00 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
"THE MECHANISM OF THOUGHT: CONFABULATION"Dr. Robert Hecht-Nielsen
University of California at San DiegoWednesday, April 26, 20062:30 – 4:00 pmGerontology AuditoriumRefreshments will be served after the talkAbstract:The talk presents a fast parallel winner-take-all competition process called confabulation [1 – 3] as the fundamental mechanism of cognition—from vision and hearing to movement and reasoning. Confabulation theory models thinking as a process in which multiple confabulations interact and in which vast numbers of items of relevant knowledge (links between neuron clusters) apply in parallel. Such a multiconfabulation begins with billions of distinct but viable conclusions and ends with a single winning conclusion. The talk will discuss the engineering, mathematical, and neuroscientific aspects of (non-Bayesian) confabulation and suggest related next steps in the development of AI and thalamo-cortical neuroscience.1. Hecht-Nielsen, R., "Cogent Confabulation," Neural Networks 18:111–115, 2005.
2. Hecht-Nielsen, R., "Mechanization of Cognition," in Y. Bar-Cohen, ed., Biomimetics (pp. 57–128), Boca Raton, FL: CRC Press.
3. Hecht-Nielsen, R., "Replicator Neural Networks," Science 269:1860–1863, 1995.Bio:Dr. Robert Hecht-Nielsen is the Director of UC San Diego's Confabulation Neuroscience
Institute, an adjunct professor in UCSD's Department of Electrical and Computer Engineering,
an IEEE Fellow, a recipient of the IEEE Neural Networks Pioneer Medal, a founder of UCSD's Graduate Program in Neurobiology, a member of UCSD's Institute for Neural Computation, author of the text NeuroComputing, and co-founder of HNC Software and the publicly traded Fair-Isaac Corporation.Host: Professor Bart Kosko, x06242, kosko@usc.edu
Location: Ethel Percy Andrus Gerontology Center (GER) -
Audiences: Everyone Is Invited
Contact: Rosine Sarafian
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor.
