Professor Emeritus of Electrical and Computer Engineering
- Doctoral Degree, Electrical Engineering, Purdue University
- Master's Degree, Electrical Engineering, University of Minnesota - Minneapolis
Ph.D. in Electrical Engineering, 1982, Purdue, West Lafayette, IN.
Michel Dubois is a Professor in the Department of Electrical Engineering of the University of Southern California. Before joining U.S.C. in 1984, he was a research engineer at the Central Research Laboratory of Thomson-CSF in Orsay, France. His main interests are Computer Architecture and Parallel Processing, with a focus on multiprocessor architecture, performance, and algorithms.
He has published more than 120 technical papers on computer architecture and algorithms(including 39 journal papers). Ten papers were published in the International Symposium on Computer Architecture (ISCA), a premier conference in computer architecture. He has edited two books, one on multiprocessor caches and one on scalable shared memory multiprocessors.
He is well-known in the field of architecture (and well referenced in the literature) for his early contributions (with Christoph Scheurich) to the problem of coherence, synchronization and memory access order in shared-memory multiprocessors.
From 1993 to 2001 he led the RPM Project, a project funded by the National Science Foundation. RPM stands for "Rapid Prototyping engine for Multiprocessors" and is a hardware platform used to implement multiprocessor systems with widely different architectures.
Dubois holds a PhD from Purdue University, an MS from the University of Minnesota, and an engineering degree from the Faculte Polytechnique de Mons in Belgium, all in Electrical Engineering. He is a member of the ACM and an IEEE Fellow.
My research area is in Computer Architecture.
I have done research in memory and processor architectures.
My long-time research interests --and main area of expertise-- have been in memory systems, especially for multiprocessors.
Early in my career I focussed on cache coherence and memory consistency models.
Nowadays I am focussed on reliability of caches and memories both in uniprocessors and multiprocessors. This research includes both the modeling of faults as well as new schemes to protect memory in power- and performance-efficient ways.
- 2005 ACM Fellow
- 1999 IEEE Fellow