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Events for April 06, 2006
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ELECTRICAL ENGINEERING-DISTINGUISHED LECTURER SERIES
Thu, Apr 06, 2006 @ 02:00 PM - 03:00 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
"Design in the Nano-Meter Regime: From Devices to System Architecture"Prof. Kaushik RoyRoscoe H. George Professor of ECECo-Director, Center for Wireless Systems & ApplicationsPurdue UniversityAbstract:Scaling of technology over the last few decades has produced an exponential growth in computing power of integrated circuits and an unprecedented number of transistors integrated into a single. However, scaling is facing several problems – severe short channel effects, exponential increase in leakage current, increased process parameter variations, and new reliability concerns. Hence, reliable, low-power designs require a shift in design paradigm. We believe that /device aware circuit and architecture design/ along with statistical design techniques can provide large improvement in power dissipation while providing the required reliability and yield. In this talk I will present device aware CMOS design to address power and reliability problems in scaled technologies for different application domains – high-performance with power as constraint and ultra-low power with reasonable performance.Bio:Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor and holds the Roscoe H. George Professor of Electrical & Computer Engineering. His research interests include VLSI design/CAD for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. Dr. Roy has published more than 350 papers in refereed journals and conferences, holds 8 patents, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim). Host: Prof. Massoud Pedram, ext. 04458 http://viterbi.usc.edu/calendar/
Location: Ethel Percy Andrus Gerontology Center (GER) - ontology Auditorium
Audiences: Everyone Is Invited
Contact: Rosine Sarafian
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COMPUTER ENGINEERING SEMINAR SERIES
Thu, Apr 06, 2006 @ 02:00 PM - 03:20 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
CENG SEMINAR SERIES"Optimized Compiler Generated Code Accelerators For FPGAs "Prof. Walid NajjarComputer Science & EngineeringUniversity of California, RiversideABSTRACT:Using FPGA devices to accelerate codes might have seemed an esoteric idea a few years ago. It is quickly moving into the mainstream not only for embedded but also supercomputer applications. Speedups ranging from 10x to 1000x have commonly been reported. FPGAs are commonly programmed using hardware description languages (HDL). HDLs are behavioral in nature and not easily amenable to high-level compiler transformations. In this paper we describe ROCCC (Riverside Optimizing Configurable Computing Compiler) a C to VHDL compiler that targets the automatic generation of FPGA-based accelerators. ROCCC optimizes and parallelizes the most frequently executed kernel loops in applications such as multimedia and scientific computing. Its objectives are to (1) bridge the performance gap between compiled and hand-written code and (2) apply extensive compile-time transformations on multi-dimensional arrays and non-trivial loop nests. Such transformations would be too complex for a human programmer to handle in a reasonable time. The objectives of the ROCCC optimizations are: (1) Maximize the parallelism in the circuit as well as the clock rate at which it operates. (2) Minimize the number of off-chip memory accesses as well as the area of the circuit. The main challenge that faces HLL to HDL translation is the paradigm shift from the stored program model to a value-based, data-driven execution – from temporal to a spatial execution. The task of an FPGA compiler is to generate both the data path and the sequence of operations (control flow) on that data path. The lack of architectural structure on the FPGA presents a number of opportunities for the compiler: (1) The parallelism is very high and limited only by the size of the FPGA or the bandwidth in or out of it. (2) On-chip storage can be configured at will. (3) Circuit customization allows the compiler to reduce the circuit size as well as the clock duration. We use dynamic programming applications, for DNA and protein string matching, to demonstrate the potentials of ROCCC. A relatively small C code that is mapped to the FPGA available on the Cray XD1 can achieve 1 to 100 Giga cell update per second. This translates to a two to four orders of magnitude speedup compared to a 2 GHz CPU with an ideal cache and no pipeline stalls.BIO:Walid A. Najjar is a Professor in the Department of Computer Science and Engineering at the University of California Riverside. He received a B.E. in Electrical Engineering from the American University of Beirut in 1979 and the M.S. and Ph.D. in Computer Engineering from the University of Southern California in 1985 and 1988 respectively. He was on the faculty of the Department of Computer Science at Colorado State University (1989 to 2000), before that he was with the USC-Information Sciences Institute. His research is in computer architecture, reconfigurable and embedded systems and compiler optimizations and has been supported by NSF, DARPA and various companies. He has served on the program committees for a number of leading conferences in this area including CASES, ISSS-CODES, DATE, HPCA, and MICRO.Host: Prof. Viktor Prasanna, x04483
Location: Olin Hall of Engineering (OHE) - -136
Audiences: Everyone Is Invited
Contact: Rosine Sarafian
