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Events for November 05, 2012
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Student Seminar Series
Mon, Nov 05, 2012 @ 12:00 PM - 02:00 PM
Ming Hsieh Department of Electrical and Computer Engineering
University Calendar
The Student Seminar Series will allow students to practice their research talks by presenting to one another. Ph.D. students will present their research to fellow Ph.D. students at each seminar session, and each student will be able to gain feedback from their peers.
The MHI Ph.D. Scholars will give presentations at the 1st Student Seminar Series event on 11/5 and explain the structure. Then students could sign up for student seminars, which will be bi-weekly.
Invited: Electrical Engineering Ph.D. students (student organized event)
11/5 Presentation:
Speaker: Osonde Osoba, Electrical Engineering Ph.D. student
Talk Title: Noisy Expectation-Maximization and Some Applications
Talk Abstract: The expectation-maximization (EM) algorithm is an iterative maximum-likelihood estimation scheme for corrupted data. Many generic statistical estimation methods are EM algorithms in disguise. I will talk about the Noisy Expectation-Maximization (NEM) algorithm. This is a modification of the EM scheme that achieves faster average convergence times than the regular EM algorithm. I will describe the theory behind the NEM algorithm. Then I will talk about some of the applications of the NEM algorithm.
Refreshments will be provided
https://mhi.usc.edu/events/event-details/?event_id=899645
More Information: 11 5 12 seminar (2).pdf
Location: Hughes Aircraft Electrical Engineering Center (EEB) - 248
Audiences: EE PhD students & postdocs
Contact: Danielle Hamra
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Yield improvement and test cost reduction for TSV based 3D stacked ICs
Mon, Nov 05, 2012 @ 01:30 PM - 02:30 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Speaker: Dr. Said Hamdioui, Delft University of Technology
Talk Title: Yield improvement and test cost reduction for TSV based 3D stacked ICs
Abstract: The industry is preparing itself for three-dimensional stacked ICs (3D-SICs), vertically interconnected by means of Through-Silicon Viaâs (TSVs). 3D-SIC is an emerging technology that promises huge advantages such as heterogeneous integration with higher performance and lower power dissipation at a smaller footprint. However, for 3D integration to become a viable product approach, many challenges have to be solved including design, manufacturing and test. The talk will provide first an overview about the opportunities and challenges of 3D-SICs. Thereafter, some major challenges such as yield improvement, test cost reduction and reliability will be addressed in more details. Compound yield is a major concern for Wafer-to-Wafer 3D stacking (used for e.g. dies with similar size such as memories), especially for higher number stacked dies. 3D-SIC test needs complex test flow trade-offs due to e.g. huge different test moments (e.g., pre-bond test, mid-bond test, final test). Finally, Reliability is another concerns that may be caused due to wafer thinning, TSV processing, thermal and mechanical stress, etc.
Biography: Hamdioui (http://www.ce.ewi.tudelft.nl/hamdioui/) received the MSEE and PhD degrees (both with honors) from the Delft University of Technology (TUDelft), Delft, The Netherlands. He is currently co-leading dependable-nano computing research activities within the Computer Engineering Laboratory of TUDelft. Prior to joining TUDelft, Hamdioui worked for Intel Corporation (CA, USA), Philips Semiconductors R&D (France) and for Philips/ NXP Semiconductors (Nijmegen, The Netherlands). His research interests include dependable nano-computing and VLSI Design & Test (defect/fault tolerance, reliability, hardware security, Design-for-Testability, Built-In-Self-Test, 3D stacked IC test, memory test, defect oriented test, etc.).
Host: Prof. Sandeep Gupta
Location: Hughes Aircraft Electrical Engineering Center (EEB) - 349
Audiences: Everyone Is Invited
Contact: Annie Yu
