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Stacked and Packed

Stacked and Packed Nanowires Hold Triplexed Megadata

April 22, 2004 —

A novel transistor architecture using nanowire memory cells the size of molecules promises more compact data storage than any existing system.

Researchers at the University of Southern California and the NASA Ames Research Center have successfully tested a self-assembled molecular memory device they say has the potential of holding 40 gigabits of data per square centimeter -- a far greater density than any achieved on silicon.

Chongwu Zhou, an assistant professor in the USC Viterbi School department of electrical engineering, said that because of the self-assembly feature, the ultra dense memory devices could be less expensive than the silicon flash memories now widely used in digital cameras, "memory sticks" and other applications.

According to a recent paper in Applied Physics Letters (APL) by Zhou and his group, the density is achieved by the nanoscale (one millionth of a millimeter) size of the building blocks used.

In the USC/Ames system is still more compact because each memory cell holds three bits of data instead of one, by virtue of having eight separate, stable identifiable electronic states. The system is already quite stable, holding information up to 600 hours.

"We believe further work can increase the stability still further," said Zhou.

The USC/Ames researchers synthesized nanowires of indium oxide that are 10 nanometers in diameter and about 2000 nanometers long, by a "laser ablation" process. They first vaporize a compound containing indium and then in a catalyzed process precipitate out the indium. The wires form spontaneously as the indium reacts with ambient oxygen.

The researchers place the nanowires on a thin layer of quartz, and activate them by submerging them in a solutions of redox materials -- various were tested. All react with the wires to self-assemble a layer of coating onto the wires creating transistors. By using different electrical voltages, the resulting transistors could be stimulated to go into three distinct activated states.

"We repeated tens of cycles for the endurance test for each memory operation and found that all the levels were distinguishable in the tested cycles," the authors wrote in their APL paper.

In their paper, the researchers also noted that their cold assembly process "represents a significant departure from the channel hot electron injection commonly used for silicon flash memory." Their paper further claims that the USC/Ames process requires lower power and is inherently less likely to introduce defects that can cause errors in the device.

Besides Zhou, the team included USC Viterbi School of Engineering graduate students Chao Li, Bo Lei, Daihua Zhang, Son Han, Tao Tang, Xialei Lu and Zuqin Liu. Team members from NASA Ames were Wendy Fan, Sylvia Asano, Jie Han and Meyya Meyyappan. Fan, Asano, and Han's contributions were underwritten by the Eloret Corporation, a Sunnyvale, Calif. Consulting firm working under contract to NASA.

Besides NASA, the National Science Foundation supported the research.