A year ago, USC engineer Chongwu Zhou described a new way to
"grow" orderly arrays of carbon nanotubes on sapphire. A new
publication this year describes a way to roll these arrays up off the
sapphire into neat parcels of working transistors ready to insert into
large-scale integrated electronic systems.
Zhou, of the USC Viterbi School of Engineering's department of
electrical engineering's says the new approach "has great potential for
high density large scale integrated systems based on carbon nanotubes
for both micro and flexible electronics publication." His description
is published in Nano Letters Vol. 6 No 1.
Nanotubes — ultrasmall hollow cylinders with walls just one
carbon atom thick — have attracted wide attention since their first
synthesis a decade and a half ago, as investigators realized they could
potentially function in integrated circuits like devices made from
carbon's periodic table first cousin silicon.
Exploitation of this possibility has been held back because previously
nanotubes have had to be grown on silicon substrates, which have
electrochemical properties that interfere with those of the
nanotubes. "Parasitic capacitance" is the term used to describe the
Instant transistors: when the array of gold-titanium gates go down
on top of the aligned nanotubes , the result is a n array of
Additionally, earlier methods required "registration" —
elaborate, difficult, expensive, and not very successful efforts
to make sure the nanotubes grew in useful configurations, or removal of
those not where they should be.
Zhou's earlier breakthrough work established that nanotubes naturally
grew in useful configurations, regular, side-by-side on some
surfaces of sapphire crystals — on two of the four planes of the
crystal (see diagram 1)
The new work builds on those findings, demonstrating the making of
nanotubes into transistors right on top of the sapphire surface. The
method is the well-established photolithography process, creating an
array of source-drain pairs, which are dropped down on top of the
nanotubes perpendicular to the parallel nanotubes.
"This … process delivered a high yield of potential devices," reported
Zhou in the paper. "Electrical measurements of the source/drain
electrode pairs revealed that 98% of the devices were connected by
carbon nanotubes and exhibited significant conduction."
Even better, "we found that there was no conduction or cross-talking
between adjacent devices. This can be understood easily because almost
all the nanotubes were aligned in the vertical direction [see picture]
… hence no conductive path could be found between the devices in one
Transistor arrays on sapphire are striking as a demonstration, but the
crystal is not the ideal substrate. Better instead is an insulator, a
plastic surface that doesn't conduct at all, like the plastics some
silicon devices are built upon.
But now Zhou believes nanotubes on insulator (NOI) architectures are possible
as well, and that may be the most far-reaching implication of the paper. Zhou found that, once the nanotubes were
Roll-off: after depositing a film of insulator on the sapphire, embedded nanotubes can taken off.
deposited on the
sapphire, his team could deposit a thin layer of plastic insulator on
top of them.
Zhou subsequently peeled this film off the sapphire -- and the
nanotubes came up with the film. The Titanium-gold gate arrays then
drop right on top of the insulator-embedded nanotubes — and Zhou's
paper describes other circuitry that can be deposited on top of that.
Zhou's team included Xiaoolei Liu and Song Han. The research was
supported by two separate NSF grants, including a CAREER award; plus
SRC award, and funds from the DARPA MolAps Program.