Anyone who has ever toasted the top of their legs with their laptop or broiled their ear on a cell phone knows that microelectronic devices can give off a lot of heat. These devices contain a multitude of transistors, and although each one produces very little heat individually, their combined thermal output is significant and can damage the device.
Thermal management is an ongoing struggle for the electronics industry as there is currently no way to accurately measure temperature at the scale of individual microelectronic devices. Overheating is an even bigger problem for the roomfuls of servers needed in data storage.
Although their small size helps make transistors and other microelectronic devices useful, it foils attempts to determine which areas in the device are hottest. The mere introduction of a probe, typically larger than the microelectronic device itself, affects the device’s temperature and precludes an accurate reading. As a result, microelectronic device manufacturers must rely on simulations alone to understand the temperatures inside individual devices.
“If you just simulated the temperature in a microelectronic device, the next thing you want to do is measure the temperature and see if you’re right,” said Matthew Mecklenburg, a senior staff scientist at the University of Southern California’s Center for Electron Microscopy and Microanalysis (CEMMA). “But a persistent question has been how to make these measurements.”
Associated with the USC Viterbi School of Engineering and the USC Dana and David Dornsife College of Letters, Arts and Sciences, USC CEMMA provides research tools for imaging, visualization, and analysis of nano-scale features and structures.
In a paper published in Science on February 6, a research team led by Mecklenburg and Chris Regan of University of California Los Angeles (UCLA), presented findings that are a major step forward in understanding temperatures in microelectronic devices.
To avoid altering the device’s temperature they decided to forego a thermometric probe altogether. They realized that the material being imaged could act as its own thermometer.
All materials change volume depending on their temperature. Therefore, a material’s temperature can be determined by carefully measuring its volume, or equivalently, its density. In this case, aluminum was used because its thermal expansion is relatively large.
To measure its density the team aimed the imaging beam from a transmission electron microscope (TEM) at the aluminum, which caused the charges within the aluminum to oscillate. These charge oscillations, or plasmons, have long been known to shift depending on a material’s density, but until now they had not been analyzed carefully enough to extract a local temperature measurement. Using the TEM and electron energy loss spectroscopy (EELS), the team was able to quantify the energy of the aluminum plasmon and precisely determine its temperature with nanometer-scale resolution.
“Every semiconductor manufacturer measures the size of their devices in transmission electron microscopes,” said Mecklenburg. “Now, in the same microscope, they can measure temperature gradients in an individual device.”
Named Plasmon Energy Expansion Thermometry (PEET), this new technique can be used to effectively measure the temperatures within a transistor by measuring the expansion of materials already contained in the device.
“This technique is sensitive to the bulk material, not just the surface,” said Mecklenburg. “Measurements of temperatures hidden inside a device will enable better thermal management, which means faster transistors and lower power consumption: your cell phone will hold its charge longer.”
The research team also included USC Viterbi associate professor Stephen Cronin and electrical engineering doctoral student Rohan Dhall, along with William Hubbard and E.R. White of UCLA and Shaul Aloni of the Lawrence Berkeley National Laboratory.
The team will next translate this technique to other materials including silicon, a staple in transistors. Many common metals and semiconductors have the proper characteristics that will allow them to serve as their own thermometers. By applying PEET to other materials used in CPUs and transistors, researchers will be able to accurately map temperatures in microelectronic devices while they are in operation, as well as develop more efficient CPUs and transistors that dissipate less heat.
This study was supported by the National Science Foundation (NSF) (DMR-126849) and in part by FAME, one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by Microelectronics Advanced Research Corporation (MARCO) and Defense Advanced Research Projects Agency (DARPA). Data for this research was acquired at CEMMA, University of Southern California. Work at the Molecular Foundry, Lawrence Berkeley National Laboratory, was supported by the U.S. Department of Energy (DE-AC02-05CH11231).
This composite image shows density (grey) and temperature (color) maps of a 100 nm-wide polycrystalline aluminum wire. The temperature is computed from the density using aluminum's known thermal expansion. Lower densities appear at crystal-grain boundaries, which are atomic-scale features, and where thermal expansion has caused the aluminum to expand. One end of the wire (green) is near room temperature, and the other (orange) is 160 K warmer. (Credit: USC CEMMA & UCLA Regan Group)
In this artist's conception of plasmon energy expansion thermometry (PEET), the focused electron beam is shown penetrating a 100-nm wide, heated aluminum wire atop a thin glass window. The electron beam has sufficient spatial resolution to detect atomic-scale grain boundaries in the poly-crystalline aluminum. (Credit: USC CEMMA & UCLA Regan Group)
This composite image stack shows a miniaturization progression relating the macroscale experimental platform to the final, nanoscale thermal image. From the bottom the stack shows: (1) a thumb and forefinger holding a printed circuit board (PCB) next to a traditional glass bulb thermometer, (2) the silicon chip on the PCB, (3) the silicon nitride membrane window in the silicon chip, and (4) a temperature map of a heated aluminum wire on the membrane window. The sizes scales of the images are roughly 2 cm, 2 mm, 30 um, and 1.5 um, respectively. The images were acquired with a hand-held camera, an optical microscope, bright field transmission electron microscopy (TEM), and plamson energy expansion thermometry (PEET) respectively. (Credit: USC CEMMA & UCLA Regan Group)
About the USC Viterbi School of Engineering
Engineering Studies began at the University of Southern California in 1905. Nearly a century later, the Viterbi School of Engineering received a naming gift in 2004 from alumnus Andrew J. Viterbi, inventor of the Viterbi algorithm now key to cell phone technology and numerous data applications. Consistently ranked among the top graduate programs in the world, the school enrolls more than 6,500 undergraduate and graduate students, taught by 180 tenured and tenure-track faculty, with 62 endowed chairs and professorships. http://viterbi.usc.edu
Megan Hazle – 213-821-1887 or email@example.com