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Conferences, Lectures, & Seminars
Events for April
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Center of Autonomy and AI, Center for Cyber-Physical Systems and the Internet of Things, and Ming Hsieh Institute Seminar Series
Wed, Apr 06, 2022 @ 02:00 PM - 03:00 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Speaker: Aaron Johnson, Mechanical Engineering at Carnegie Mellon University
Talk Title: The Trouble with Contact: State Estimation and Control Generation for Discontinuous Systems
Series: Center for Cyber-Physical Systems and Internet of Things
Abstract: Contact with the outside world is challenging for robots due to its inherently discontinuous nature -- when a foot or hand is touching a surface the forces are completely different than if it is just above the surface. However, most of our computational and analytic tools for planning, learning, and control assume continuous (if not smooth or even linear) systems. Simple models of contact make assumptions (like plasticity and coulomb friction) that are known to not only be wrong physically but also inconsistent. In this talk I will present techniques for overcoming these challenges in order to adapt smooth methods to systems that have changing contact conditions. In particular I will focus on two topics: First, I will present the "Salted Kalman Filter" for state estimation over hybrid systems. Second, I will show a few techniques for generating new controllers with changing contact conditions, using both higher-order direct collocation and hybrid iLQR.
Biography: Prof. Johnson is an Assistant Professor in Mechanical Engineering at Carnegie Mellon University, working on legged robots, adaptive controls, contact-rich manipulation, physics based planning & learning, and terrain manipulation as director of the Robomechanics Lab. Previously, his postdoc focused on convergent manipulation planning algorithms in the Personal Robotics Lab at Carnegie Mellon University. He received his PhD in 2014 on self-manipulation and dynamic behaviors on legged robots (among other things) in Kod*lab at the University of Pennsylvania. He is the recipient of the NSF Career award, the ARO Young Investigator Award, and the CMU George Tallman Ladd Research Award.
Host: Pierluigi Nuzzo and Feifei Qian
Webcast: https://usc.zoom.us/webinar/register/WN_zyIBh_1gQLmKpMJG0GyLxwLocation: Online
WebCast Link: https://usc.zoom.us/webinar/register/WN_zyIBh_1gQLmKpMJG0GyLxw
Audiences: Everyone Is Invited
Contact: Talyia White
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor. -
ECE-EP Seminar - Jae-sun Seo, Friday, April 8th at 10am via Zoom
Fri, Apr 08, 2022 @ 10:00 AM - 11:00 AM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Speaker: Jae-sun Seo, Arizona State University
Talk Title: Energy-Efficient AI Chip Designs with Digital and Analog Circuits
Abstract: AI algorithms have been widespread across many practical applications, e.g. convolutional neural networks (CNNs) for computer vision, long short-term memory (LSTM) for speech recognition, etc., but state-of-the-art algorithms are compute-/memory-intensive, posing challenges for AI hardware to perform inference and training tasks with high throughput and low power consumption, especially on area-/energy-constrained edge devices.
In this talk, I will present our recent research of several energy-efficient AI ASIC accelerators on both all-digital chips and analog/mixed-signal circuit based chips. These include (1) a 40nm CNN inference accelerator with conditional computing and low external memory access, (2) a 28nm CNN training accelerator exploiting dynamic activation/weight sparsity, and (3) a 28nm programmable in-memory computing (IMC) inference accelerator integrating 108 capacitive-coupling-based IMC SRAM macros. We will discuss the digital/analog circuits and architecture design, as well as hardware-aware algorithms employed for the proposed energy-efficient AI accelerators. Based on the demonstrated advantages and challenges of digital and analog AI chip designs, emerging research directions for new AI hardware with new device/circuit/architecture/algorithm design considerations will be discussed.
Biography: Jae-sun Seo received the Ph.D. degree from the University of Michigan, Ann Arbor in 2010. From 2010 to 2013, he was with IBM T. J. Watson Research Center, working on the DARPA SyNAPSE project and next-generation processor designs. Since 2014, he has been with Arizona State University, where he is currently an Associate Professor in the School of ECEE. He was a visiting faculty at Intel Circuits Research Lab in 2015. His research interests include efficient hardware design of machine learning algorithms and neuromorphic computing. Dr. Seo was a recipient of IBM Outstanding Technical Achievement Award (2012), NSF CAREER Award (2017), and Intel Outstanding Researcher Award (2021). He has served on the technical program committees for ISSCC, MLSys, DAC, DATE, ICCAD, etc.
Host: ECE-Electrophysics
More Information: Jae-sun Seo Flyer.pdf
Audiences: Everyone Is Invited
Contact: Marilyn Poplawski
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor. -
CILQ Internal Seminar
Fri, Apr 08, 2022 @ 12:00 PM - 01:00 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Speaker: Keith Chugg, Professor, USC
Talk Title: Co-Design of Algorithms and Hardware for Deep Neural Networks
Abstract: Neural networks are in wide use in cloud computing platforms. This includes inference and training with the latter typically performed on programmable processors with multiply-accumulate (MAC) accelerator arrays (e.g., GPUs). In many applications, it can be describable to train on an edge device or using energy efficient application specific circuits. In this talk I will present some research results on application specific hardware acceleration methods for neural networks. Pre-defined sparsity is a method to reduce the complexity of training and inference. In contrast to pruning approaches which remove edges/weights during or after training, this approach sets a pre-defined pattern of sparse connection prior to training and holds this pattern fixed during training and inference. This allows one to design the pattern of sparsity to match a specific hardware acceleration architecture. We also consider Logarithmic Number Systems (LNS) for implementation of training. With LNS, operations are performed on the log of the quantities and therefore multiplies are simplified to addition while additions are more complex in the log domain. We present some preliminary results for LNS training and highlight ongoing challenges in applying this to larger, more complex networks. In many of these approaches we borrow from the design and implementation of iterative decoders for digital communication systems.
Host: CILQ
Webcast: https://usc.zoom.us/j/92417517950?pwd=WUkycy90cndVQko5R3RhQ1U3STBDdz09More Information: ChuggSeminar-Apr8-2022.pdf
Location: via zoom
WebCast Link: https://usc.zoom.us/j/92417517950?pwd=WUkycy90cndVQko5R3RhQ1U3STBDdz09
Audiences: Everyone Is Invited
Contact: Corine Wong
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor. -
ECE-EP Seminar - Jie Gu, Monday, April 11th at 9am via Zoom
Mon, Apr 11, 2022 @ 09:00 AM - 10:00 AM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Speaker: Jie Gu, Northwestern University
Talk Title: Efficient On-chip Neural Architecture and Data Processing in the Era of Domain-specific Computing and AI
Abstract: In this new era of data-driven domain-specific computing, the integrated circuits, serving as the cornerstones of modern electronic devices, are facing tremendous challenges in meeting the ever-growing data processing demand under staggering technology improvement. It is clear that conventional Von-Neumann architecture is no longer sufficient for the ubiquitous AI and many newly-arrived complex computing tasks. As a result, it is critical to look for new computing architecture that delivers the most efficient computing and data processing solutions. In this talk, I will first discuss our recent developments of a special "neural CPU" processor at the conjunction of Von-Neumann and deep learning architectures to establish a new computing platform where general-purpose computing is incorporated into the framework of deep learning accelerators achieving significant end-to-end performance enhancement and data movement reduction. Second, I will discuss efficient data processing solutions for domain-specific computing using examples of a sparse convolutional neural network accelerator for 3D/4D point-cloud image classification and efficient data processing for wirelessly powered human machine interface System-on-Chip (SoC) with embedded machine learning capabilities. Demonstrations of test chips using standard CMOS process will be used to show the benefits of the proposed solutions in comparison with the conventional implementations.
Biography: Jie Gu is currently an associate professor in Northwestern University. He received his B.S. degree from Tsinghua University, M.S. degree from Texas A&M University and Ph.D. degree from University of Minnesota. From 2008 to 2010, he was with Texas Instruments, Dallas, TX on research and developments of ultra-low voltage mobile processors for smartphones. From 2011 to 2014, he was with Maxlinear leading developments of home multi-media broadband SoC chips. He joined ECE department in Northwestern University from 2015 working on novel circuit and architecture for low power microprocessors and machine learning accelerators. He is a recent recipient of NSF CAREER award.
Host: ECE-Electrophysics
More Info: https://usc.zoom.us/j/93576256328?pwd=OUlzMFYxVzVTY1cwNit5NFR6Nmdmdz09
More Information: Jie Gu Flyer.pdf
Audiences: Everyone Is Invited
Contact: Marilyn Poplawski
Event Link: https://usc.zoom.us/j/93576256328?pwd=OUlzMFYxVzVTY1cwNit5NFR6Nmdmdz09
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor. -
Center of Autonomy and AI, Center for Cyber-Physical Systems and the Internet of Things, and Ming Hsieh Institute Seminar Series (Part 1)
Wed, Apr 13, 2022 @ 02:00 PM - 02:30 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Speaker: Prakash Sarathy, Northrop Grumman Global Products (1st Speaker)
Series: Center for Cyber-Physical Systems and Internet of Things
Abstract: Increasing tempo and complexity of missions for aircraft and space vehicles has driven the design of such systems to higher levels of autonomous operations. Consequently, the challenges of ensuring a safe and secure operational regime have been rapidly escalating. While a number of techniques, new and old, are available to address different facets of these challenges, what seems to be missing is some cohesive approach or framework that can support the total design lifecycle while lowering the cost and risk of a successful design and deployment of such cyber-physical systems.
This talk will focus on some of these challenges and where overlaps exist in the safety and security needs and in its eventual resolution within a software and hardware design. Some notable approaches and methodologies will be discussed briefly to highlight the potential of such convergence as well as some mention of current state-of-practice in software and hardware verification, validation, and accreditations (VV&A).
Biography: Dr. Prakash Sarathy is the Chief Engineer for common mission processing subsystem for Northrop Grumman Global Products center. He earned his doctoral degree in Aerospace Engineering from Syracuse University. He has held positions as post-doctoral fellow, research engineer and tenured engineering faculty in his prior career. He has over 30 years of experience in the area of software applied to aerospace engineering, providing technical and project/program management and oversight for advanced technology programs requiring accelerated risk burn down and rapid maturation. His technical expertise areas include cooperative distributed architectures for multi-agent systems, cooperative decision frameworks, agent architectures for mission management, aggregate control of distributed assets, user interface design for aggregate level situational awareness. Insertion of neural networks, evolutionary computing and emergent behavior to decision making paradigms. This software engineering expertise coupled with his in-depth experience in linear and nonlinear dynamics of vehicle systems, applied to guidance, navigation and control of aircraft, spacecraft, and robots as well as of real-time and embedded simulations, high fidelity modeling, implementation, VV&A, formal methods, and testing, provide an excellent framework for the challenges of next generation autonomous aircraft. He has spearheaded an effort to assemble a feasible set of methodologies to establish bounded behavior assurance for advanced autonomous missions under contested operating conditions.
Host: Pierluigi Nuzzo, nuzzo@usc.edu
Webcast: https://usc.zoom.us/webinar/register/WN_zyIBh_1gQLmKpMJG0GyLxwLocation: Online
WebCast Link: https://usc.zoom.us/webinar/register/WN_zyIBh_1gQLmKpMJG0GyLxw
Audiences: Everyone Is Invited
Contact: Talyia White
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor. -
Center of Autonomy and AI, Center for Cyber-Physical Systems and the Internet of Things, and Ming Hsieh Institute Seminar Series (Part 2)
Wed, Apr 13, 2022 @ 02:30 PM - 03:00 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Speaker: Marlon Marquez, Northrop Grumman Space Systems (2nd Speaker)
Series: Center for Cyber-Physical Systems and Internet of Things
Abstract: Increasing tempo and complexity of missions for aircraft and space vehicles has driven the design of such systems to higher levels of autonomous operations. Consequently, the challenges of ensuring a safe and secure operational regime have been rapidly escalating. While a number of techniques, new and old, are available to address different facets of these challenges, what seems to be missing is some cohesive approach or framework that can support the total design lifecycle while lowering the cost and risk of a successful design and deployment of such cyber-physical systems.
This talk will focus on some of these challenges and where overlaps exist in the safety and security needs and in its eventual resolution within a software and hardware design. Some notable approaches and methodologies will be discussed briefly to highlight the potential of such convergence as well as some mention of current state-of-practice in software and hardware verification, validation, and accreditations (VV&A).
Biography: Marlon Marquez is a Consulting Engineer at NG Space Systems. Mr. Marquez has prior experience designing with Intel, Power PC, and ARM microprocessor technologies. He has domain knowledge with state-of-the- art cyber security and anti-tamper infrastructures including TPMs, secure hypervisor technologies and multi-level security concepts. He has experience with Operating System technologies, Pub/Sub application development, and Kernel development. He is an FPGA subject matter expert and has extensive experience with FPGA and Processor interfaces. He holds two USPTO patents and presented ASIC technology at IEEE. He has a BSEE from UCLA, was an MS candidate at Cal State Northridge in Electrical and Computing Engineering and has an MBA from Pepperdine University.
Host: Pierluigi Nuzzo, nuzzo@usc.edu
Webcast: https://usc.zoom.us/webinar/register/WN_zyIBh_1gQLmKpMJG0GyLxwLocation: Online
WebCast Link: https://usc.zoom.us/webinar/register/WN_zyIBh_1gQLmKpMJG0GyLxw
Audiences: Everyone Is Invited
Contact: Talyia White
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor. -
Center of Autonomy and AI, Center for Cyber-Physical Systems and the Internet of Things, and Ming Hsieh Institute Seminar Series
Wed, Apr 20, 2022 @ 02:00 PM - 03:00 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Speaker: Bichen Wu, Meta (former Facebook) Reality Labs
Talk Title: Efficient Deep Learning for Computer Vision
Series: Center for Cyber-Physical Systems and Internet of Things
Abstract: Deep neural networks are empowering increasingly more applications in computer vision. To deploy deep learning to more devices (edge, mobile, AR/VR glasses), we need to tackle numerous challenges to make deep learning more efficient. In this talk, we will focus on two important aspects of efficiency: model efficiency and data efficiency. Improving model efficiency enables packing stronger AI capabilities to devices with limited compute, while better data efficiency unblocks more applications constrained by lack of data. This talk will first introduce the FBNet series of work [1-4], which studies neural architecture search (NAS) methods to automatically develop compute-efficient models to achieve better accuracy-efficiency trade-offs. For data efficiency, this talk will introduce OTTER [5], a data-efficient algorithm that uses language to train vision models to recognize images in a zero-shot manner -- being able to recognize new classes without needing extra labels.
Papers related to this talk:
[1] FBNetV1: Wu, Bichen, et al. "Fbnet: Hardware-aware efficient convnet design via differentiable neural architecture search." Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition. 2019.
[2] FBNetV2: Wan, Alvin, et al. "Fbnetv2: Differentiable neural architecture search for spatial and channel dimensions." Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition. 2020.
[3] FBNetV3: Dai, Xiaoliang, et al. "FBNetV3: Joint Architecture-Recipe Search using Neural Acquisition Function." arXiv preprint arXiv:2006.02049 (2020).
[4] FBNetV5: Wu, Bichen, et al. "FBNetV5: Neural Architecture Search for Multiple Tasks in One Run."
[5] OTTER: Wu, Bichen, et al. "Data Efficient Language-Supervised Zero-Shot Recognition with Optimal Transport Distillation."
Biography: Dr. Bichen Wu is a research scientist at Meta (former Facebook) Reality Labs. His research is focused on efficient deep learning algorithms, models, and systems, aiming to bring AI capabilities to massive edge devices and applications. His paper on Neural Architecture Search -- FBNet, is among the top 0.01% highest cited computer science papers published in 2019. He obtained his Ph.D. from Berkeley AI Research, UC Berkeley and his Bachelor of Engineering from Tsinghua University in 2013.
Host: Pierluigi Nuzzo, nuzzo@usc.edu
Webcast: https://usc.zoom.us/webinar/register/WN_zyIBh_1gQLmKpMJG0GyLxwLocation: Online
WebCast Link: https://usc.zoom.us/webinar/register/WN_zyIBh_1gQLmKpMJG0GyLxw
Audiences: Everyone Is Invited
Contact: Talyia White
This event is open to all eligible individuals. USC Viterbi operates all of its activities consistent with the University's Notice of Non-Discrimination. Eligibility is not determined based on race, sex, ethnicity, sexual orientation, or any other prohibited factor.
