Events Calendar

ECE Seminar Announcement: Accelerating Chip-Building Design Cycles for Future Generations of Computing

Speaker: Dr. Christopher Torng, Postdoctoral Researcher, Stanford University

Talk Title: Accelerating Chip-Building Design Cycles for Future Generations of Computing

Abstract: The chip building industry is a major cornerstone of the global economy. As a result, addressing the causes behind a multi-year global chip shortage is important for both near and long term futures. Unfortunately, one major challenge is that it is difficult to produce high-quality designs quickly and at low cost using traditional hardware design flows. This means that the industry wastes valuable fabrication slots learning painful design lessons rather than meeting economic demands.

My research focuses on building new architectures, systems, and design tools to accelerate chip building design cycles for future generations of computing systems. To support this goal, my research spans across the computing stack, ranging from applications, compilers, architectures, and down to chip implementation. In this talk, I will first present a set of vertically integrated techniques (compiler, architecture, and VLSI) that significantly reduces the design effort for extremely fine-grain power control in spatial architectures. Next, I will introduce my work on a new generation of open and agile hardware flow tools that leverage modern programming language features to increase code reuse in physical design. Finally, I will discuss recent work on Amber SoC, a coarse-grained reconfigurable array designed with an end-to-end agile accelerator-compiler co-designed flow. I will conclude with my future directions in supporting chip building for the next generation of computing.

Biography: Christopher Torng is a postdoctoral researcher at Stanford University. He received his Ph.D. degree, M.S. degree, and B.S degree (2019, 2016, 2012) in Electrical and Computer Engineering from Cornell University. His projects target the development of architectures and tools to accelerate building chips and complex hardware systems. His tools have achieved use across multiple universities to support over ten academic tapeouts in technologies ranging from 180nm to 16nm. His activities have resulted in a selection as a Rising Star in Computer Architecture (2018) by Georgia Tech and an IEEE MICRO Top Pick from Hot Chips (2018).

Host: Dr. Peter Beerel, pabeerel@usc.edu

Webcast: https://usc.zoom.us/j/99531222900?pwd=S1VDR2pRU2lyZ2hORmtObE1PcFh6Zz09

Location: Hughes Aircraft Electrical Engineering Center (EEB) - 248

WebCast Link: https://usc.zoom.us/j/99531222900?pwd=S1VDR2pRU2lyZ2hORmtObE1PcFh6Zz09

Audiences: Everyone Is Invited

Contact: Mayumi Thrasher