Fri, Sep 30, 2022 @ 02:00 PM - 03:00 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Speaker: Wanghua Wu, Samsung Semiconductor Inc.
Talk Title: Recent Trends and Advances in High Performance Fractional-N PLL Design
Series: Integrated Systems
Abstract: any advanced
electronic systems. In recent years, both analog and all-digital PLLs employing sampling or sub-sampling phase detector have gained popularity and demonstrated below 100-fs integrated jitter and superior figure-of-merit. This talk focuses on this PLL architecture and elaborates the advanced design techniques
to achieve low jitter, low fractional spurs, fast locking, and low power operation. Both circuit design and digital calibration techniques will be presented in detail. In addition, recent advances in reference clock generation will also be discussed as it is crucial for high performance PLLs.
Biography: Dr. Wanghua Wu received the B.Sc. degree from Fudan University, Shanghai, China, in 2004, M.Sc. degree and Ph.D. degree from Delft University of Technology, The Netherlands in 2007 and 2013, respectively, all in electrical engineering. From 2013 to 2016, she was an RFIC Design Engineer in Marvell, developing high performance frequency synthesizers for WLAN transceivers. Since 2016, she has been with Samsung Semiconductor Inc. USA. She is currently a Principal Engineer and Senior Manager, leading advanced cellular RFIC design. Her research interest is on CMOS frequency synthesis for wireless applications. She currently serves as the Technical Program Committee member of IEEE International Solid-State Circuits Conference (ISSCC), Custom Integrated Circuits Conference (CICC), and Radio Frequency Integrated Circuits Symposium (RFIC).
Host: MHI - ISSS, Hashemi, Chen and Sideris
More Info: Meeting ID: 926 7347 1681, Passcode: 960345
More Information: Abstract and Bio-Sept 30-Wu.pdf
Audiences: Everyone Is Invited
Contact: Marilyn Poplawski
Event Link: Meeting ID: 926 7347 1681, Passcode: 960345