Events Calendar

CS Colloquium: Christopher Torng (USC / ECE) - Accelerating Chip-Building Design Cycles for Future Generations of Computing

Speaker: Christopher Torng, USC / ECE

Talk Title: Accelerating Chip-Building Design Cycles for Future Generations of Computing

Series: Computer Science Colloquium

Abstract: The chip building industry is a major cornerstone of the global economy. Unfortunately, it is difficult to produce high-quality designs quickly and at low cost using traditional hardware design flows. This makes it challenging for the community to build new performant and efficient domain-specific accelerators in a timely manner, especially as areas such as machine learning continue to quickly evolve. This talk focuses on new architectures, systems, and design tools to accelerate chip building design cycles for future generations of computing systems. Specifically, we will explore a set of vertically integrated techniques (compiler, architecture, and VLSI) to significantly reduce the design effort to build a coarse-grain reconfigurable array (CGRA) architecture, a flexible architectural template that can be specialized towards many different application domains. I will also introduce an end-to-end agile accelerator-compiler co-designed flow to iteratively evolve such systems across multiple generations of hardware accelerators.

This lecture satisfies requirements for CSCI 591: Research Colloquium

Biography: Christopher Torng is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Southern California. Prior to his appointment, he was a postdoctoral researcher at Stanford University from 2019 to 2022 operating in the leadership of the Stanford AHA Agile Hardware Project, where he worked on creating high-performance and energy-efficient architectures for domain-specific hardware acceleration supported by an agile software-hardware co-design methodology. He received his Ph.D. degree from Cornell University in electrical and computer engineering in 2019. He has over ten years of experience building complex digital SoCs as ASIC prototypes as well as new agile flow tools that have already supported tapeouts for at least 12 academic chips, implemented in technologies from 180nm to 12nm. His activities have resulted in his selection as a Rising Star in Computer Architecture (2018) by Georgia Tech as well as an IEEE MICRO Top Pick from Hot Chips (2018).

Host: CS Department

Location: Olin Hall of Engineering (OHE) - 136

Audiences: Everyone Is Invited

Contact: CS Faculty Affairs