Events Calendar

EE-EP Seminar, Jae-Sun Seo, Friday, January 22nd at 2:00pm in EEB 132

Speaker: Jae-sun Seo, Arizona State University

Talk Title: Designing Power-Efficient Neuromorphic VLSI Systems That Can Learn and Infer

Abstract: In recent years, both industry and academia have shown large interest in low-power hardware designs for neuromorphic computing (e.g. TrueNorth) and machine learning algorithms (e.g. convolutional neural networks) for a wide range of image, speech, and biomedical applications. State-of-the-art algorithms are computation-/memory-/communication-intensive, however, making it difficult to perform low-power real-time training and classification. Furthermore, to optimize system-level power, efficient power delivery and voltage regulation of such VLSI systems also becomes a critical concern.

In this talk, I will present our exemplary research on low-power digital neuromorphic processor design with on-chip learning, as well as workload-adaptive integrated voltage regulators. I will discuss our work on on-chip STDP (spike-timing dependent plasticity) learning for pattern recognition (45nm), spiking clustering for deep-brain sensing (65nm), and a versatile neuromorphic processor design that can support various STDP learning / inhibition rules found in neuroscience literature with large fan-in/out per neuron. To provide an efficient and stable power supply for such processors against fluctuating workloads, integrated switched-capacitor voltage regulator designs are proposed with fast on-chip current sensing (32nm) and capacitance dithering (65nm).

I will also briefly discuss our machine learning hardware designs for speech and biometric applications, and present future research directions to vertically integrate and further improve the power-efficiency of neuromorphic systems while bridging the gap with machine learning approaches.



Biography: Jae-sun Seo received his Ph.D. degree from the University of Michigan in 2010 in electrical engineering. From 2010 to 2013, he was with IBM T. J. Watson Research Center, where he worked on neuromorphic chip design for the DARPA SyNAPSE project and energy-efficient circuits for IBM's high-performance processors. Since January 2014, he has been with Arizona State University as an assistant professor in the School of ECEE. During the summer of 2015, he was a visiting faculty at Intel Circuits Research Lab. His research interests include efficient hardware design of learning algorithms and integrated power management. He received the IBM outstanding technical achievement award in 2012, and serves on the technical program committee for ISLPED and the organizing committee for ICCD.

Host: EE-EP

Location: Hughes Aircraft Electrical Engineering Center (EEB) - 132

Audiences: Everyone Is Invited

Contact: Marilyn Poplawski