Events Calendar

Energy Efficient Memory Circuits: From IoT to Exascale Systems and Beyond

Speaker: Dr. Jaydeep Kulkarni, Staff Research Scientist, Circuit Research Scientist, Circuit Research Lab, Intel Corporation

Talk Title: Energy Efficient Memory Circuits: From IoT to Exascale Systems and Beyond

Abstract: With the rapid advances in computing systems spanning from billions of IoTs (Internet of Things) to high performance exascale super computers, energy efficient design is an absolute must. It is projected that by 2020, around 50 billion internet connected devices will be deployed generating hundreds of zettabytes (1021 bytes) of data. It is estimated that embedded memories can occupy up to 70% of the die area in these devices. These trends clearly indicate the paramount importance of developing energy efficient, dense memory circuits and systems across the entire compute continuum. I will present two energy efficient memory solutions one geared for IoT systems while the other targeted at high performance exascale systems. With extremely low energy budget, IoT systems would need ultralow voltage circuits for always-ON sensing and computing. Low voltage Static Random Access Memory (SRAM) operation is challenging due to conflicting read-stability vs write-ability requirements. I will present two Schmitt Trigger based SRAMs having built-in process variation tolerance for extreme low voltage operation. Measurement results from 130nm test-chips confirm successful operation up to 150mV [JSSC'07, TVLSI'12]. At the other end of compute spectrum consisting of high performance exascale systems, fixed voltage/ frequency guardbands are applied to the nominal operating specifications to guarantee reliable operation in the presence of temperature variations, voltage supply droops, and transistor aging induced degradation. Since most of the systems operate at nominal conditions, the necessary guardbands for these infrequent dynamic variations significantly limit the system energy efficiency. I will present adaptive and resilient domino register file design techniques to realize a unified framework for logic + memory operating on same voltage/frequency domain. Measurement results from a 22nm test-chip demonstrate 21% higher throughput with 67% improved energy efficiency [ISSCC'15, JSSC'16]. I will conclude the seminar by highlighting the interesting areas in memory research for the development of next generation of energy efficient computing systems. These aspects include emerging non-volatile technologies such as STT, and RRAM memories, memory scaling using monolithic 3D integration, logic-in-memory organization / architectures for non von Neumann computing models such as neuromorphic computing, and security/privacy issues in next zettabytes of data.

Biography: Jaydeep P. Kulkarni received the Bachelor of Engineering (B.E.) degree from the University of Pune, India in 2002, the Master of Technology (M. Tech.) degree from the Indian Institute of Science (IISc) Bangalore, India in 2004 and Ph.D. degree from Purdue University, West Lafayette, IN, in 2009 all in electrical engineering. During 2004-05, he worked as a Design Engineer at Cypress Semiconductors, Bangalore and designed I/O circuits for micro-power SRAMs. He joined Circuit Research Lab (CRL) at Intel Corporation, Hillsboro, OR in 2009, where he is currently working as a staff research scientist. His research is focused on energy efficient integrated circuits and systems. He has filed 27 patents and published 52 papers in referred journals and conferences (1500 citations).
Dr. Kulkarni received 2004 Best M. Tech Student Award from IISc Bangalore, 2008 SRC Inventor Recognition Awards, 2008 ISLPED Design Contest Award, 2008 Intel Foundation Ph.D. Fellowship Award, 2008 SRC TECHCON best paper in session award, 2010 Purdue School of ECE Outstanding Doctoral Dissertation Award, 2012 Intel patent recognition award, six Intel Divisional Recognition Awards for successful technology transfers, 2015 IEEE Circuits and Systems Society's Transactions on VLSI systems best paper award, and 2015 Semiconductor Research Corporation's (SRC) outstanding industrial liaison award. He has participated in technical program committees of A-SSCC, ISLPED, ISCAS, and ASQED conferences. He serves as an associate editor for IEEE Transactions on VLSI Systems, and as an industrial liaison at the SRC, NSF Visual Cortex on Silicon program, Stanford System-X alliance, Stanford-NMTRI and SONIC STARnet research program. He is a senior member of IEEE.

Host: Professor Peter Beerel

Location: 248

Audiences: Everyone Is Invited

Contact: Suzanne Wong