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  • EE-EP Faculty Candidate, Shimeng Yu, Friday, April 6th at 2pm in EEB 132

    Fri, Apr 06, 2018 @ 02:00 PM - 03:30 PM

    Ming Hsieh Department of Electrical and Computer Engineering

    Conferences, Lectures, & Seminars

    Speaker: Shimeng Yu, Arizona State University

    Talk Title: Neuro-Inspired Computing with Resistive Synaptic Devices

    Abstract: Resistive device is a two-terminal electronic device based on oxides/chalcogenides that can switch its resistance under programming voltage. This technology has made significant progresses in the past decade as a competitive candidate for the next generation non-volatile memory (NVM), namely resistive random access memory (RRAM). In this presentation, I will discuss its new applications in the context of neuro-inspired computing, as it has a great potential to serve as the synaptic devices in the neuromorphic hardware such as machine/deep learning accelerators. First, I will discuss the desired characteristics of the resistive synaptic devices (e.g. analog multilevel states, weight tuning linearity, variation/noises) and oscillation neuron devices, and show the representative device prototypes of offline training and online training. Next, I will introduce the crossbar array architecture to efficiently implement the weighted sum and weight update operations that are commonly used in the machine/deep learning algorithms, and show the array-level experimental demonstrations for these key operations such as the convolution kernel. Then I will introduce "NeuroSim", a device-circuit-algorithm co-design framework to evaluate the impact of non-ideal device effects on the neuromorphic system performance (i.e. learning accuracy) and trade-offs in the circuit-level performance (i.e. area, latency, energy). Last, I propose to possible future research directions including new materials and device engineering for achieving linear weight update, binarizing neural network algorithm by allowing binary memory cells and our efforts in chip-scale tape-out of a XNOR-Net accelerator with SRAM and heterogeneous integration of RRAM on top of CMOS. This presentation will be concluded with a holistic view of my research vision from materials/device engineering, and circuit/architecture co-optimization for neuro-inspired computing with emerging nanoelectronic devices.

    Biography: Shimeng Yu received the B.S. degree in microelectronics from Peking University, Beijing, China in 2009, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, USA in 2011, and in 2013, respectively. He is currently an assistant professor of electrical engineering and computer engineering at Arizona State University, Tempe, AZ, USA.
    His research interests are emerging nano-devices and circuits with a focus on the resistive memories for different applications including machine/deep learning, neuromorphic computing, monolithic 3D integration, hardware security, radiation-hard electronics, etc. He has published >70 journal papers and >100 conference papers with citations >5500 and H-index 34.
    Among his honors, he is a recipient of the DOD-DTRA Young Investigator Award in 2015, the NSF Faculty Early CAREER Award in 2016, the ASU Fulton Outstanding Assistant Professor in 2017 and the IEEE Electron Devices Society Early Career Award in 2017.
    He served the Technical Program Committee for IEEE International Symposium on Circuits and Systems (ISCAS) 2015-2017, ACM/IEEE Design Automation Conference (DAC) 2017-2018, and IEEE International Electron Devices Meeting (IEDM) 2017-2018, etc.

    Host: EE-Electrophysics

    Location: Hughes Aircraft Electrical Engineering Center (EEB) - 132

    Audiences: Everyone Is Invited

    Contact: Marilyn Poplawski


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