Events Calendar

A Process Variation Perspective on 3D Integration

Siddharth Garg,
Carnegie-Mellon UniversityAbstract:
3D integration is a promising emerging technology that offers increased system integration by vertically integrating multiple planar die. In addition, 3D integration provides lower communication latency and greater bandwidth between system components, potentially addressing the increased on-chip communication costs that accompany technology scaling. However, emerging technologies must also be critically evaluated to identify potential pitfalls. From this perspective, the elevated thermal profile of 3D integrated circuits (ICs) has already been identified as a cause for concern. In this talk, I will demonstrate that the impact of manufacturing process variations on the performance of 3D circuits is another emerging cause for concern and discuss promising solutions to this problem.I will begin by presenting 3D-GCP, a high-level model for the impact of process variations on 3D IC performance. Using this model I will show that, in fact, 3D ICs suffer greater performance degradation under the impact of process variations compared to equivalent 2D implementations.
Furthermore, the performance hit is more severe as the number of layers in the 3D stack is increased, potentially eliminating any of performance benefits of 3D integration. Motivated by these predictions, I will present a novel process variation aware 3D assembly strategy that uses post-fabrication test data to maximize the number of assembled systems that meet a specified performance target. Experimental results on both application-specific and general purpose multi-core platforms demonstrate that significant performance yield improvements are achieved using the proposed techniques.Biography:
Siddharth Garg is currently a post-doctoral fellow in the Electrical and Computer Engineering Department at Carnegie-Mellon University. He received in a Ph.D. in Electrical and Computer Engineering also from CMU, a Masters degree in Electrical Engineering from Stanford University and a Bachelors degree in Electrical Engineering from the Indian Institute of Technology
(IIT) Madras. In the summer of 2007, he interned at the AMD micro-architecture power and performance modeling group.
His research interests include design methodologies and tools for reliability and energy-aware multi-processor architectures and 3D integration technology. He has won a best paper at the ISQED
2009 and the SRC TECHCON 2009, and a best paper award nomination at DATE 2009.

Location: Hughes Aircraft Electrical Engineering Center (EEB) - -248

Audiences: Everyone Is Invited

Contact: Estela Lopez