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Architectural and Circuit-Level Design Techniques for Power and Temperature Optimizations in On-Chip

Hosted by Prof Timothy M. PinkstonSpeaker: Houman Homayoun, University of California, IrvineAbstract:
In order to reduce register file's peak temperature in an embedded processor, we propose RELOCATE: an architectural solution which redistributes the access pattern to physical registers through a novel register allocation mechanism. The goal is to keep some partitions unused (idle) and cooling down. The temperature of idle partitions is further reduced by power gating them into destructive sleep mode to reduce their leakage power. The redistribution mechanism changes the active region periodically to modulate the activity within the register file and prevent the active region from heating up excessively. Our approach resulted in an average reduction of 8.3°C in the register file's peak temperature for standard benchmarks.Also, recent studies have shown that peripheral circuits, including decoders, wordline drivers, input and output drivers, contribute a large fraction of the overall cache leakage. In addition, as technology migrates to smaller geometries, leakage contribution to total power consumption increases faster than dynamic power, indicating that leakage will be a major contributor to overall power consumption. This work also proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor's on-chip caches by targeting leakage in cache peripheral circuits. Experimental results indicate that the proposed techniques can keep the L1 cache peripherals in one of the low-power modes for more than 85% of total execution time, on average. This translates to an average leakage power reduction of 50% for 65nm technology. The DL1 cache energy-delay product is reduced, on average, by 20%. The overall processor power is reduced by up to 8.7% (an average of 5.3%). Biography:
Houman Homayoun is a PhD student in the department of computer science at the University of California, Irvine. His research is on power-temperature and reliability-aware memory and processor design optimizations and spans the areas of computer architecture and circuit design. From 2006 to 2007 he was working in Novelics, a leading provider of system-on-chip (SoC) embedded memory, where he was the principle architect of a parametrizable BIST microprocessor. The chip was successfully taped-out and delivered in 130, 90 and 65nm. Homayoun received his BS degree in electrical engineering in 2003 from Sharif University of Technology, Tehran, Iran. He received his MS degree in computer engineering in 2005 from University of Victoria, Canada.

Location: Hughes Aircraft Electrical Engineering Center (EEB) - -248

Audiences: Everyone Is Invited

Contact: Janice Thompson