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  • Low Cost – Highly Accurate Timer for Embedded and Networked Systems

    Fri, Sep 17, 2010 @ 11:00 AM - 12:00 PM

    Ming Hsieh Department of Electrical and Computer Engineering

    Conferences, Lectures, & Seminars


    Speaker: Dr. Young Cho, USC-Information Sciences Institute

    Talk Title: Low Cost – Highly Accurate Timer for Embedded and Networked Systems

    Abstract: Time synchronization is an important service for networked and embedded systems.  High quality timing information allows embedded network nodes to provide accurate time-stamps, fast localization, efficient duty cycling schedules, and other essential functions. In this presentation, I will present a new type of local clock source called Crystal Compensated Crystal based Timer (XCXT) and the novel algorithms that use the timer to (1) obtain highly stable concept of time, (2) retain low-power operation, and (3) automatically calibrate the nodes in a network.  The XCXT has timing stabilities similar to the timers based on temperature compensated crystal oscillators (TCXO) but has a lower implementation cost and requires less power. I will present the initial 8MHz prototype XCXT unit made with Tmote. Using the simplest algorithm, the XCXT achieves an effective frequency stability of ±1ppm and consumes only 1.27mW. On the other hand, commercially available TCXOs with similar stability can cost over 10 times as much and consume over 20mW. I will also describe an enhanced algorithm that improves the XCXT's power consumption up to 50% depending on the target application and environmental conditions. Then, I will describe an algorithm that will allow XCXT equipped network nodes to quickly, automatically, and adaptively calibrate the timer.  This algorithm not only ensures high timing accuracies for all the nodes, it provides resilience to other common problem seen in other types of oscillators, such as crystal aging.  Finally, I will discuss some of the recent work that seeks to apply the concept to CMOS based oscillators.  Successful transition may have significant impact on the way CMOS devices are clocked. Preliminary findings indicate promising results.

    Biography: Young Cho is a research scientist at Division 7 of University of Southern California - Information Sciences Institute.  He is also research assistant professor at CS department of USC.  Given his academic and industrial experience in high performance computer architecture and networking, he is currently leading a number several research efforts that surrounding field programmable gate arrays (FPGA) applications and wireless sensor network; especially that of underwater sensing.  He has three patents and over 30 conference and journal publications in computer network security, FPGA based applications, and wireless sensor networks. Prior to joining USC-ISI in September of 2008, he conducted research as a visiting professor at Washington University in St. Louis from 2005-2007 where he led a high performance data clustering project and as a post-doctoral scholar at UCLA where he led a research in high stability timers for wireless sensor network in 2007-2008.  He received his PhD in Electrical Engineering from UCLA, MS in Computer Engineering from UT Austin, and BA in Computer Sciences from UC Berkeley.  Between his BA and MS, he worked as an engineer for a start-up company, Myricom Inc., for three years to design high performance networking products as well as automatic target recognition system funded by Department of Defense.

    Host: Dr. Alexander A. Sawchuk

    Location: Hughes Aircraft Electrical Engineering Center (EEB) -

    Audiences: Everyone Is Invited

    Contact: Mayumi Thrasher

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