Events Calendar

Technology-Aware Circuit Design of Low Power Robust Memories for Future Processors

Speaker: Sumeet Kumar Gupta,

Talk Title: Technology-Aware Circuit Design of Low Power Robust Memories for Future Processors

Abstract: The past few decades have seen the evolution of the semiconductor industry driven by technology scaling. However, as conventional MOSFETs are scaled further, exponential increase in leakage and higher sensitivity to process variations are expected to pose severe challenges. This has led to the exploration of alternate technologies and computing paradigms. In order to harness the full potential of the emerging technologies, there is a strong need for design methodologies which utilize the unique technology features to achieve lower power, higher performance and increased robustness of VLSI circuits and systems. In my talk, I will discuss our work on device-circuit co-design techniques for low power robust memories in emerging technologies, with a focus on FinFET-based SRAMs. We have developed a mixed mode simulation framework for device-circuit analysis of FinFET-based circuits and I will share some key features of this simulator. I will highlight the importance of exploring device-circuit interactions and show how technology-circuit co-optimization leads to expansion of the design space of 6T SRAMs. We have proposed asymmetric FinFET devices and tri-mode independent gate FinFETs, which achieve mitigation of design conflicts in 6T SRAMs. A detailed discussion on low power robust SRAM design using these devices will be presented. I will also discuss the possibilities of using emerging memory technologies like spin-transfer torque (STT) MRAM in on-chip caches, based on our ‘devices to systems’ simulation framework. I will end my talk by highlighting my future research directions and possibilities in modeling and device-circuit co-design of emerging technologies.

Biography: Sumeet Kumar Gupta received B. Tech degree in Electrical Engineering from Indian Institute of Technology, Delhi, India in 2006 and M.S. in Electrical and Computer Engineering from Purdue University, West Lafayette, IN in 2008. He is currently pursuing Ph.D. degree at the school of Electrical and Computer Engineering at Purdue University, West Lafayette, IN.

He was an intern at National Semiconductor, Advanced Micro Devices Inc. and Intel Corporation in
2005, 2007 and 2010, respectively. His research interests include low power variation aware VLSI circuit
design, nano-electronics and spintronics, device-circuit co-design and nano-scale device modeling and
simulations. He has published over 20 articles in refereed journals and conferences.

Mr. Gupta was the recipient of the Magoon Award and the Outstanding Teaching Assistant Award
from Purdue University in 2007 and Intel PhD Fellowship Award in 2009. He has also received a
certificate of recognition for an outstanding job during the summer internship by Intel Labs and
certificates of merit for excellent academic performance at IIT Delhi.


Host: Professor Viktor K. Prasanna

Location: Hughes Aircraft Electrical Engineering Center (EEB) -

Audiences: Everyone Is Invited

Contact: Janice Thompson