Events Calendar

Integrated Systems Seminar Series

Speaker: Dr. Jafar Savoj, Xilinx

Talk Title: Design of High-Speed Wireline Transceivers for Backplane Communications in 28nm CMOS

Abstract: This presentation describes the design of the architecture and circuit blocks for backplane communication transceivers. A channel study investigates the major challenges in the design of high-speed reconfigurable transceivers. Architectural solutions resolving channel-induced signal distortions are proposed and their effectiveness on various channels is investigated.
Subsequently, the presentation describes the design of two fully-adaptive backplane transceivers embedded in state-of-the-art low-leakage 28nm CMOS FPGAs operating up to 12.5Gb/s and 13.1Gb/s. The receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation. A speculative DFE removes the immediate post-cursor ISI. The second transceiver also uses a 4-tap sliding DFE to remove the post-cursor ISI up to 64 taps. Both CTLE and DFE are fully adaptive using sign-sign LMS algorithm. A novel clocking technique uses wideband LC and ring oscillators for reliable clocking for 0.6-12.5Gb/s and 0.6-13.1Gb/s operation. The transmitter utilizes a 3-tap FIR and provides flexibility for supply and ground referenced operation. The two transceivers achieve BER < 10-15 over a 33dB-loss backplane at 12.5Gb/s, and over a 31dB-loss backplane at 13.1Gb/s. Both transceivers achieve BER < 10-15 over channels with 10G-KR characteristics at 10.3125Gb/s.


Biography: Jafar Savoj received the B.Sc. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1996, and the M.Sc. and Ph.D. degrees in electrical engineering from the University of California, Los Angeles, in 1998 and 2001, respectively.

Dr. Savoj’s areas of expertise include technology and product development for wireless, wireline, and analog systems. He is currently an Engineering Director with the Serdes Technology Group at Xilinx, San Jose, CA, and leads high-speed, low-power wireline transceiver development for FPGA applications. From 2008 to 2010, he was with Qualcomm, Santa Clara, CA, and led the advanced technology development group for wireless connectivity. He was responsible for development of WLAN and Near Field Communication (NFC) transceivers, and low power chip-to-chip interfaces for mobile platforms. From 2005 to 2008, he was a principal engineer at Rambus, where he developed ultra-high-speed data converters for software programmable wireline transceivers. Prior to that, he held design engineering positions at Marvell Semiconductor, Santa Clara, CA, focusing on fiber channel and Gigabit Ethernet transceivers; and at Transpectrum, Los Angeles, CA, architecting 10-Gb/s and 40-Gb/s optical transceivers in CMOS technology. He held a lecturing position at Stanford University in 2004. He is the author of High-Speed CMOS Circuits for Optical Receivers (Kluwer, 2001).

Dr. Savoj was a recipient of the IEEE Solid-State Circuits Society Predoctoral Fellowship for 2000–2001, and the Beatrice Winner Award for Editorial Excellence at the 2001 ISSCC, and the Design Contest Award of the 2001 Design Automation Conference. He serves as a technical program committee member of ISSCC (Analog Subcommittee). He served as a technical program committee member of the IEEE Custom Integrated Circuits Conference (CICC) from 2001 to 2007 and the IEEE Symposium on VLSI Circuits from 2007 to 2011. He was an Associate Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS from 2008 to 2011 and a Guest Editor for the Journal in 2005, 2006 and 2011.


Host: Prof. Hossein Hashemi, Prof. Mahta Moghaddam, Prof. Mike Chen

More Info: http://mhi.usc.edu/activities/integrated-systems

More Information: Savoj_sep14_flyer2.pdf

Location: Hughes Aircraft Electrical Engineering Center (EEB) - 248

Audiences: Everyone Is Invited

Contact: Hossein Hashemi

Event Link: http://mhi.usc.edu/activities/integrated-systems