Events Calendar

Yield improvement and test cost reduction for TSV based 3D stacked ICs

Speaker: Dr. Said Hamdioui, Delft University of Technology

Talk Title: Yield improvement and test cost reduction for TSV based 3D stacked ICs

Abstract: The industry is preparing itself for three-dimensional stacked ICs (3D-SICs), vertically interconnected by means of Through-Silicon Via’s (TSVs). 3D-SIC is an emerging technology that promises huge advantages such as heterogeneous integration with higher performance and lower power dissipation at a smaller footprint. However, for 3D integration to become a viable product approach, many challenges have to be solved including design, manufacturing and test. The talk will provide first an overview about the opportunities and challenges of 3D-SICs. Thereafter, some major challenges such as yield improvement, test cost reduction and reliability will be addressed in more details. Compound yield is a major concern for Wafer-to-Wafer 3D stacking (used for e.g. dies with similar size such as memories), especially for higher number stacked dies. 3D-SIC test needs complex test flow trade-offs due to e.g. huge different test moments (e.g., pre-bond test, mid-bond test, final test). Finally, Reliability is another concerns that may be caused due to wafer thinning, TSV processing, thermal and mechanical stress, etc.

Biography: Hamdioui (http://www.ce.ewi.tudelft.nl/hamdioui/) received the MSEE and PhD degrees (both with honors) from the Delft University of Technology (TUDelft), Delft, The Netherlands. He is currently co-leading dependable-nano computing research activities within the Computer Engineering Laboratory of TUDelft. Prior to joining TUDelft, Hamdioui worked for Intel Corporation (CA, USA), Philips Semiconductors R&D (France) and for Philips/ NXP Semiconductors (Nijmegen, The Netherlands). His research interests include dependable nano-computing and VLSI Design & Test (defect/fault tolerance, reliability, hardware security, Design-for-Testability, Built-In-Self-Test, 3D stacked IC test, memory test, defect oriented test, etc.).

Host: Prof. Sandeep Gupta

Location: Hughes Aircraft Electrical Engineering Center (EEB) - 349

Audiences: Everyone Is Invited

Contact: Annie Yu