Events Calendar

Integrated Systems Seminar Series

Speaker: Dr. Gerhard Sollner, Raytheon Company

Talk Title: Aging Treatments for CMOS Analog and Digital Circuits

Abstract: One beauty of Complementary Metal-oxide-Silicon (CMOS) transistors is that the carriers travel between source and drain in a nearly atomically smooth channel in the semiconductor adjacent to the oxide gate insulator. However, as device dimensions shrink, electric fields increase, carriers travel at higher velocities, and any imperfections in the channel-oxide interface become increasingly important.
CMOS transistors age when high-speed carriers in the channel break chemical bonds and dislodge atoms at the oxide-semiconductor interface. These uncompensated bonds are charged. They change the gate potential necessary to attract charges to the channel, that is, they change the threshold voltage. In addition, they act as scattering centers for carriers in the channel. These scattering centers reduce carrier mobility, which in turn reduces several parameters important to circuit performance such as gain and the maximum frequency of operation.
In this talk we will look carefully at the two most important physical processes of CMOS aging. It turns out that one is most important for digital circuits, the other is most important for analog circuits. Then, after a brief introduction to how aging processes are accelerated (so that you don’t have to measure for 10 years to predict a 10-year lifetime), we will show expressions from the literature that predict how these aging processes depend on temperature , electric fields, and time, for any CMOS device technology. Then some of our recent measurements on 65-nm digital devices will be described, along with their agreement with the literature.
The ultimate goal of this work is to develop anti-aging techniques, i.e. healing for CMOS circuits that undergo aging. To this end we designed several circuits, both analog and digital, in 45-nm CMOS. These all include internal circuits that measure the effects of aging and other circuits that adjust transistor biases to cure the aging and return the circuit to the performance level for which it was designed. To tie all this together, we will describe an algorithm that has demonstrated excellent results when finding the optimum bias levels in multi-dimensional nonlinear cases such as these.
The bottom line: we will show that aging effects can seriously degrade circuit performance. The cure is to either over-design the circuit, which reduces performance, or to apply anti-aging techniques, which result in compact, efficient circuits with high performance.


Biography: Dr. Sollner joined the Advanced Technology group at Raytheon Company in November 2009 where he now manages several programs. Before his current position Gerry founded and was CEO of a company, Kenet Inc, which successfully developed families of very-low-power analog-to-digital converters based on technology invented in his group at MIT Lincoln Laboratory. Kenet was acquired by Intersil Corporation. Prior to starting Kenet, Gerry spent 20 years at Lincoln Laboratory, leading the Analog Device Technology Group for his last 10 years there. In 1997 he was elected to Fellow of the IEEE for "his work in resonant-tunneling structures and contributions to understanding of high-speed semiconductor devices." Dr. Sollner has published over 50 articles in peer-reviewed journals, has given over 30 invited lectures, and holds 8 patents.

Host: Prof. Hossein Hashemi and Prof. Mike Chen

Location: Hughes Aircraft Electrical Engineering Center (EEB) - 248

Audiences: Everyone Is Invited

Contact: Hossein Hashemi