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  • Ph.D. Defense: "Thermal Analysis and Multiobjective Optimization for Three Dimensional Integrated Circuits"

    Mon, Jul 15, 2013 @ 03:00 PM - 05:00 PM

    Ming Hsieh Department of Electrical and Computer Engineering

    Conferences, Lectures, & Seminars


    Speaker: Fatemeh Kashfi, PhD Student, Electrical Engineering, USC Viterbi School of Engineering

    Talk Title: THERMAL ANALYSIS AND MULTIOBJECTIVE OPTIMIZATION FOR THREE DIMENSIONAL INTEGRATED CIRCUITS

    Abstract: Three Dimensional Integrated Circuit (3DIC) technology has been introduced to address the interconnect issues in nanometer circuit design that limit performance improvement and power reduction. However, stacking active layers of silicon leads to increased power density and overall higher temperatures in a 3D chip implementation for many designs. New thermal map modeling, and temperature measurement, mitigation and management techniques should be introduced for this technology. In this dissertation we study the thermal correlation between the stacked layers in 3DICs. We then propose a fast and efficient 3D thermal map modeling based on scaled hotspot areas, depending on the distance of a stacked layer from the heatsink and also thermal effects of the layers on each other. The efficiency of the proposed modeling is demonstrated with its use in a thermal sensor distribution algorithm. We also show that the thermal sensor distribution algorithm should be solved as a 3D problem. We furthermore propose a new 3D design for thermal sensor circuits to be shared between layers in a 3DIC.

    We also study different methods of multiobjective optimization to find the optimum operating point of a VLSI circuit. We provide wide mathematical analyses of different multiobjective optimization techniques for this purpose. We also study the difference of convex and non-convex modeling of the objectives in the multiobjective optimization algorithms. We apply our multiobjective optimization methods to optimize three conflicting objectives of cost, performance and thermal reliability to find an optimum building block placement in 3DICs. The variables for the optimization are the number of layers, area of the 3DIC, position of the building blocks, number of TSVs and total wirelength. We use our proposed fast 3D thermal map modeling to eliminate the thermal analysis bottleneck in multiobjective optimization iterations.

    Biography: Fatemeh Kashfi received her Bacholar of Sceince and Master of Science in Electrical Engineering from University of Tehran in 2005 and 2008 respectively. She joined University of Southern California in 2008 where she is currently pursuing a Ph.D. degree. From August 2010 to January of 2011, she interned at Intel Corporation in Hillsboro, Oregon. Her research interests include 3DIC design and analysis and power and thermal analysis in VLSI circuits.

    Host: Professor Jeff Draper

    Location: Hughes Aircraft Electrical Engineering Center (EEB) - 248

    Audiences: Everyone Is Invited

    Contact: Janice Thompson

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