Professor of Electrical and Computer Engineering
- Doctoral Degree, Electrical Engineering, Stanford University
- Master's Degree, Electrical Engineering, Stanford University
- Bachelor's Degree, Electrical Engineering, Princeton University
Peter Beerel received his B.S.E. degree in Electrical Engineering from Princeton University in 1989, and his M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1991 and 1994, respectively. He joined the Department of Electrical Engineering-Systems at the University of Southern California's Viterbi School of Engineering in 1994, where he is currently a Full Professor. Dr. Beerel was the Faculty Director of Innovation Studies at the USC Stevens Institute for Innovation from 2006 to 2008. In May of 2008, he took a leave of absence from USC and co-founded TimeLess Design Automation with one of his Ph.D. students, Dr. Georgios Dimou. Their mission was to demonstrate and commercialize an asynchronous ASIC flow for high-performance systems. They were successful and sold the company in July of 2010 to Fulcrum Microsystems which was acquired by Intel in 2011. In 2015, his Ph.D. student, Dylan Hand, co-founded a second company, Reduced Energy Microsystems, to commercialize an asynchronous ASIC flow for ultra-low-power vision and machine learning systems. Dr. Beerel joined REM as Chief Scientist in 2016.
Dr. Beerel's research interests include a variety of topics in CAD and asynchronous VLSI design. He has been a member of the technical program committee for the International Symposium on Advanced Research in Asynchronous Circuits and Systems since 1997, was program co-chair for ASYNC'98, and was general co-chair for ASYNC'07. Dr. Beerel was recipient of a VSoE Outstanding Teaching Award in 1997 and the VSoE Junior Research Award in 1998. He received a National Science Foundation CAREER Award and a 1995 Zumberge Fellowship. He was also co-winner of the Charles E. Molnar award for two papers published in ASYNC'97 that best bridged theory and practice of asynchronous system design, was co-recipient of the best paper award in ASYNC'99, and winner of the best paper award in ASYNC'2014. He was the 2008 recipient of the IEEE Region 6 Outstanding Engineer Award for significantly advancing the application of asynchronous circuits to modern VLSI chips.
My primary interest is in VLSI and computer-aided design for digital VLSI systems. Our primary emphasis is asynchronous and timing resilient designs, including logic and high-level synthesis, power and performance analysis, and formal verification, library development, and physical design flows. We are aggressively applying these design alternatives and CAD tools to the design of both high-performance and low-power systems. Other research projects include enhancing metrics for hardware security and the acceleration of training of sparse neural networks.
- 2011 Viterbi School of Engineering USC Faculty Service Award
- 2009 IEEE Outstanding Engineer Award, IEEE Region 6, Southern Area (2008)
- 2008 IEEE IEEE Senior Member
- 2008 IEEE Region 6, Southern Area Outstanding Engineer Award
- 2007 ASYNC-07 General Co-Chair & Finance Chair
- 2006 Other Awards
- 2000 Large-Scale NSF ITR Award Recipient
- 1999 ASYNC-99, co-author of winning paper "RAPPID: An Asynchronous Instruction Length Decoder" Best Paper Award
- 1998 USC School of Engineering Junior Faculty Research Award
- 1998 ASYNC-98 Program Co-Chair
- 1997 Philips Corporation & SUN Microsystems Charles Molnar Award
- 1997 USC School of Engineering Outstanding Teaching Award
- 1995 USC NSF Career Award
- 1995 USC Zumberge Fellow
- 1993 Stanford University Philips Fellowship
- 1989 Princeton University Charles Ira Young Memorial Tablet and Medal
- 1989 Princeton University Phi Beta Kappa, Sigma Xi, and Tau Beta Pi