Viterbi Faculty Directory

Research Summary

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The SMART Interconnects Group, headed by Timothy Pinkston, is engaged in research on technologies and techniques for achieving high-performance communication in parallel computer systems---symmetric multiprocessor systems as well as distributed network-based processing systems. Our efforts mainly focus on the interconnection network. We are developing efficient network interface and routing architectures/techniques that support high availability, reliability and quality of service. Deadlock-free adaptive routing techniques are being pursued that allow for maximum exploitation of routing freedom within the network. Network self-healing techniques are also being investigated that allow the network to dynamically self-check, reconfigure, and manage itself in the presence of expansion, hot-swapping, faults, and other anomalous conditions. We also have interest in designing, modeling and implementing high-bandwidth optical/optoelectronic-based interconnect! ion networks, network processors, and switch/router architectures. Below are some of the major contributions made thus far.

* In collaboration with others, we have developed a theory and methodology for the design of dynamic network reconfiguration techniques that result in minimal packet loss, are deadlock-free, and are generally applicable to high-performance and highly dependable interconnection networks.
* We have developed an intuitive model, a theoretical framework, and empirical simulation techniques for characterizing the causal effects of various network attributes on the formation of correlated resource dependencies and deadlock. This work provides the basis for alternative, more efficient deadlock-free routing approaches, such as deadlock recovery- based routing.
* We have introduced the idea of progressive deadlock recovery routing and have developed several fully-adaptive routing techniques for regular and irregular networks based on this approach. We have also proposed and implemented various router architecture optimizations applicable to deadlock-recovery routers.
* We have proposed and implemented portions of a hybrid cache coherence/network interconnect architecture designed to support low-latency interprocessor communication over point-to-point and broadcast optical channels.
* We have developed design methodologies and router architectures for energy-, resource-, and performance-efficient on-chip networks (a.k.a., NoCs), being among the first to explore architectural support for effectively applying power-saving techniques, such as power gating, to NoCs for reducing static power consumption. Our research contributions in this area advance fundamental understanding of how to design NoCs to enable scalable data movement with low power consumption, minimal resource requirements, and high performance.
* We have also designed, modeled and implemented several other optical/optoelectronic architectures with the collaboration of others. The theme and contribution of this work is in advancing basic research that addresses architectural issues related to the co-integration of promising optoelectronic components with highly functional logic circuitry typical of potential applications envisioned for this emerging technology, notably network routers.