SUNMONTUEWEDTHUFRISAT
Events for March 24, 2006
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Challenges in Reducing High Volume Manufacturing Test Cost for Micro-processors
Fri, Mar 24, 2006 @ 10:20 AM - 11:20 AM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
CENG SEMINAR SERIES"Challenges in Reducing High Volume Manufacturing Test Cost for Micro-processors "Dr. Sreejit ChakravartyIntelABSTRACT:This talk is aimed at a general audience who are not familiar with Microprocessor testing. The basics of high volume manufacturing (HVM) testing will be introduced. The major cost components of HVM testing and the challenges going forward will be highlighted. Detailed discussion on any given topic will be left to the Q&A session.BIO:Dr. Sreejit Chakravarty spent about 11 years in academia as an Associate Professor of Computer Science at the State University of New York at Buffalo. Since 1997 he has been with Intel Corporation where he is a Principal Engineer in the Test Technology group. He is the technical lead in various test research projects targeted at Intel's microprocessor products, including advanced fault models, various aspects of at-speed testing and PV-si correlation issues. He serves on the program and organizing committees of several IEEE conferences and has delivered several keynote addresses at IEEE sponsored conferences. Dr. Chakravarty is a Fellow of the IEEE. Host: Prof. Melvin Breuer, x04469
Location: Hughes Aircraft Electrical Engineering Center (EEB) - -248
Audiences: Everyone Is Invited
Contact: Rosine Sarafian
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Digital Circuits Using Carbon Nanotubes: Modeling, Design, and Architectures
Fri, Mar 24, 2006 @ 02:00 PM - 03:30 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
CENG SEMINAR SERIES"Digital Circuits Using Carbon Nanotubes: Modeling, Design, and Architectures "Dr. Ali KeshavarziCircuit Research Labs, IntelBSTRACT:Scaling of Silicon technology continues while research has started in other novel materials for future technology generations beyond year 2015. Carbon nanotubes (CNTs) with their excellent carrier mobility are a promising candidate. We have studied the promise that carbon nanotube-based electronics hold for digital circuit design. We investigated different carbon nanotube based field effect transistors (CNFETs) for an optimal switch. Schottky Barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs were systematically compared from a circuit/system design perspective. A simulation environment incorporating an atomistic device description and a look-up table based circuit solver has been used. The role of parasitics in CNFET design shows that performance is limited by the gate overlap capacitance and the quality of nano contacts to these promising transistors. Optimal geometries and transistor architecture have been proposed to provide maximum performance while minimizing parasitics. Analysis of high performing single tube SB CNFET transistor structures revealed 1 to 1.5 nm to be the optimum CNT diameter for high speed digital application. We determined optimal spacing and layout of CNT arrays, an architecture that is most likely required for driving capacitive loads and interconnects in digital applications. Circuit applications impact the choice of packing density in CNFET arrays. Highest packing density is required for driving large capacitive loads for example this is achieved by placing CNTs of 1 nm in diameter at 1.6nm apart in an array formation. However, if CNT arrays are driving other CNT arrays, a looser packing density will be sufficient.CNTs with their high current density, despite several serious technological barriers, show potential for performance improvement. For benchmarking purposes, we will discuss a figure of merit for evaluating CNTs. From a process technology perspective, further research is required on material quality of the CNTs, on the growth of the nanotubes in a predetermined direction with good control of diameter thickness (for control of variation), on making doped CNTs for MOS CNFETs, on fabricating CNT-based transistor arrays, and also on producing reliable nano-contacts to the nanotubesBIO:Dr. Ali Keshavarzi received his Ph.D. degree in electrical engineering from Purdue University, West Lafayette, Indiana. He is a senior staff research scientist at Circuit Research Laboratories (CRL) of Intel Corporation, Portland, Oregon. He is currently focusing on long-term research in low-power/high-performance circuit techniques and transistor device structures for future generations of microprocessors. Ali has been with Intel for thirteen years, has published more than 20 papers and has more than 30 patents (20 issued and the rest are pending patents). Ali has received the best paper award at 1997 IEEE International Test Conference at Washington, D.C. on testing solutions of intrinsically leaky integrated circuits. Ali is a member of the ISLPED & ISQED technical program committees.Host: Prof. Massoud Pedram, x04458
Location: Hughes Aircraft Electrical Engineering Center (EEB) - -248
Audiences: Everyone Is Invited
Contact: Rosine Sarafian
