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SUNMONTUEWEDTHUFRISAT
Events for May 08, 2006
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Meet USC (AM session)
Mon, May 08, 2006 @ 09:00 AM - 12:00 PM
Viterbi School of Engineering Undergraduate Admission
Workshops & Infosessions
This half day program is designed for prospective freshmen and family members. Meet USC includes an information session on the University and the Admission process; a student led walking tour of campus and a meeting with us in the Viterbi School. Meet USC is designed to answer all of your questions about USC, the application process and financial aid.Reservations are required for Meet USC. Please call the USC Admission Center at (213) 740-6616 to check availability and to make an appointment. Be sure to tell them you are interested in Engineering!
Location: USC Admission Center
Audiences: Prospective Freshman and Family Members - RESERVATIONS REQUIRED
Contact: Viterbi Admission
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Optimizing Divide-and-Conquer
Mon, May 08, 2006 @ 10:30 AM - 11:30 AM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
CENG SEMINAR SERIES"Optimizing Divide-and-Conquer Scan Test"Dr. C.P. RavikumarTexas Instruments IndiaABSTRACT:Test application time and test power are important considerations in modern-day SoC that can pack over 10 million gates. Today, the industrial practice is to make use of scan testing with on-chip compression and decompression to reduce test application time. A divide-and-conquer mechanism is used to reduce test power. However, it is rarely possible to partition the SoC in a way that can eliminate a "top-up" mode where all the scan flops are stitched into top-level scan chains. The top-up mode is intended for addressing faults in the glue logic and is often a "killer" - it can reduce the effectiveness of hierarchical test and scan test compression. In this talk, we describe two improvements over the traditional Divide-and-Conquer Scan Test to reduce test application time and test power. We illustrate the benefits of using these techniques on industrial designs.BIO:Dr. C.P. Ravikumar obtained his Ph.D. from the University of Southern California in 1991. He then joined the faculty of Electrical Engineering at IIT Delhi, where he rose from the position of Assistant Professor to Full Professor, before moving on to a position in the industry in 2000. He spent a year at Control Net India as Vice President of Training and R&D, and later joined Texas Instruments India as Senior Technologist in VLSI Test. He has published over 150 papers in international journals and conferences in the areas of Design for Test, VLSI Design, and High Performance Computing. He has made professional contributions to a number of conferences in India, including the VLSI Design Conference, VLSI Design and Test Symposium (which he founded), and the High Performance Computing conference. He is the recipient of the Best Student Paper Award at the VLSI Design Conference, the Best Paper Awards at VLSI Test Symposium and VLSI Design Conference.Host: Prof. Viktor Prasanna, x04483
Location: Hughes Aircraft Electrical Engineering Center (EEB) - -248
Audiences: Everyone Is Invited
Contact: Rosine Sarafian
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Meet USC (PM session)
Mon, May 08, 2006 @ 01:00 PM - 03:00 PM
Viterbi School of Engineering Undergraduate Admission
Workshops & Infosessions
This half day program is designed for prospective freshmen and family members. Meet USC includes an information session on the University and the Admission process; a student led walking tour of campus and a meeting with us in the Viterbi School. Meet USC is designed to answer all of your questions about USC, the application process and financial aid.Reservations are required for Meet USC. Please call the USC Admission Center at (213) 740-6616 to check availability and to make an appointment. Be sure to tell them you are interested in Engineering!
Location: USC Admission Center
Audiences: Prospective Freshman and Family Members - RESERVATIONS REQUIRED
Contact: Viterbi Admission
