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Events for July 20, 2009
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Meet USC: Admission Presentation, Campus Tour, & Engineering Talk
Mon, Jul 20, 2009
Viterbi School of Engineering Undergraduate Admission
Workshops & Infosessions
This half day program is designed for prospective freshmen and family members. Meet USC includes an information session on the University and the Admission process; a student led walking tour of campus and a meeting with us in the Viterbi School. Meet USC is designed to answer all of your questions about USC, the application process and financial aid.Reservations are required for Meet USC. This program occurs twice, once at 9:00 a.m. and again at 1:00 p.m. Please visit http://www.usc.edu/admission/undergraduate/visit/meet_usc.html to check availability and make an appointment. Be sure to list an Engineering major as your "intended major" on the webform!
Location: USC Admission Center
Audiences: Prospective Freshmen and Family Members - RESERVATIONS REQUIRED
Contact: Viterbi Admission
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Subthreshold Source-Coupled Circuit Design for Ultra-Low-Power Applications
Mon, Jul 20, 2009 @ 11:00 AM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Speaker: Yusuf Leblebici (École Polytechnique Fédérale de Lausanne)Abstract:
In this talk, a novel approach is presented for
implementing ultra-low-power digital components
and systems using source-coupled logic (SCL)
circuit topology, operating in weak inversion
(subthreshold) regime. Minimum size pMOS
transistors with shorted drain-substrate
contacts are used as gate-controlled, very high
resistivity load devices. Based on the proposed
approach, the power consumption and the
operation frequency of logic circuits can be
scaled down linearly by changing the tail bias
current of SCL gates over a very wide range
spanning several orders of magnitude, which is
not achievable in subthreshold CMOS circuits.
Measurements in conventional 0.18um CMOS
technology show that the tail bias current of
each gate can be set as low as 10 pA, with a
supply voltage of 300 mV, resulting in a
power-delay product of less than 1 fJ
(Femto-Joule) per gate. Fundamental circuits
such as ring oscillators and frequency dividers,
as well as more complex digital blocks such as
parallel multipliers designed by using the STSCL topology will be presented.Speaker Biography:Yusuf Leblebici received his Ph.D. degree in
electrical and computer engineering from the
University of Illinois at Urbana-Champaign
(UIUC) in 1990. Between 1991 and 2001, he worked
as a faculty member at UIUC, at Istanbul
Technical University, and at Worcester
Polytechnic Institute (WPI) - where he
established and directed the VLSI Design Laboratory.Since 2002, Dr. Leblebici has been a Chair
Professor at the Swiss Federal Institute of
Technology in Lausanne (EPFL), and director of
Microelectronic Systems Laboratory. He is a
coauthor of 4 textbooks, namely, "Hot-Carrier
Reliability of MOS VLSI Circuits" (Kluwer
Academic Publishers, 1993), "CMOS Digital
Integrated Circuits: Analysis and Design"
(McGraw Hill, 1st Edition 1996, 2nd Edition
1998, 3rd Edition 2002), "CMOS Multichannel
Single-Chip Receivers for Multi-Gigabit Optical
Data Communications" (Springer, 2007) and
"Fundamentals of High-Frequency CMOS Analog
Integrated Circuits" (Cambridge University
Press, 2009), as well as more than 150 articles
published in various journals and conferences.Hosted by Dr. Anthony LeviLocation: Charles Lee Powell Hall (PHE) - 631
Audiences: Everyone Is Invited
Contact: Theodore Low
