EE Seminar: Statistical and Formal Methods in Hardware Security

Speaker: Yiorgos Makris, Professor, ECE Department, The University of Texas at Dallas

Talk Title: Statistical and Formal Methods in Hardware Security

Abstract: Partly because of design outsourcing and migration of fabrication to low-cost areas around the globe, and partly because of increased reliance on third-party intellectual property, the integrated circuit (IC) supply chain is now considered far more vulnerable than ever before. With electronics ubiquitously deployed in sensitive domains and critical infrastructure, such as wireless communications, industrial environments, as well as health, financial and military applications, understanding the corresponding risks and developing appropriate remedies have become paramount. To this end, in this presentation I will discuss the role that statistical and formal methods can play in ensuring security and trustworthiness of ICs and the systems wherein they are deployed, and I will introduce two solutions that my research group has contributed to the area of hardware security.

The first contribution, known as Statistical Side-Channel Fingerprinting, is a statistical method for assessing whether an integrated circuit originates from a known distribution or not, based on parametric measurements such as delay, power, electromagnetic emanations, temperature, etc. Effectiveness of this method in detecting ICs which have been subjected to malicious modifications (a.k.a. hardware Trojans) will be demonstrated using silicon measurements from a custom-designed wireless cryptographic IC. Solutions to the main challenges of statistical side-channel fingerprinting, namely the availability of a statistically significant trusted population and the detection of hardware Trojans which are activated after deployment, will also be discussed and demonstrated in silicon.

The second contribution, known as Proof-Carrying Hardware Intellectual Property, is a formal method for proving compliance of an electronic design acquired from a third-party vendor with a set of security properties. These properties, which are expressed as theorems with corresponding proofs in a formal proof management system (i.e., Coq) and which can be automatically checked by the consumer, outline the boundaries of trusted operation without necessarily specifying the exact functionality of the design. Effectiveness of this method in certifying secure instruction execution will be demonstrated on a popular microcontroller and its utility for data secrecy protection through fully-automated information flow tracking will be demonstrated on a cryptographic core.

I will conclude by revisiting the modus operandi of the hardware security research area as it enters its second decade of activity and I will emphasize the need for (i) intensified efforts towards statistical and formal methods which can offer risk bounds and provable security, and (ii) synergy platforms whereby hardware security can be seamlessly integrated with software security, network security and cryptography, towards developing holistic system-level solutions for both contemporary and emerging applications. In this context, I will also briefly review our recent efforts in mixed-signal and system-level proof-carrying hardware, covert wireless communications, machine learning-based malware detection and workload forensics, as well as in establishing an NSF Industry/University Cooperative Research Center on Hardware and Embedded System Security and Trust (CHEST).

Biography: Yiorgos is a professor of Electrical and Computer Engineering at The University of Texas at Dallas, where he leads the Trusted and RELiable Architectures (TRELA) Research Laboratory. Prior to joining UT Dallas in 2011, he spent a decade as a faculty of Electrical Engineering and of Computer Science at Yale University. He holds a Ph.D. (2001) and an M.S. (1997) in Computer Engineering from the University of California, San Diego, and a Diploma of Computer Engineering and Informatics (1995) from the University of Patras, Greece. His main research interests are in the application of formal and machine learning-based methods in the design of trusted and reliable integrated circuits and systems, with particular emphasis in the analog/RF domain. He is also investigating hardware-based malware detection, forensics and reliability methods in modern microprocessors, as well as on-die learning and novel computational modalities using emerging technologies. His research activities have been supported by NSF, SRC, ARO, AFRL, DARPA, Boeing, IBM, LSI, Intel, Advantest, AMS and TI. Yiorgos is as an associate editor of the IEEE Transactions on Information Forensics and Security, the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, the IEEE Design & Test periodical and the Springer Journal of Electronic Testing: Theory and Applications. He served as the 2016-2017 general chair and the 2013-2014 program chair of the IEEE VLSI Test Symposium, and as a topic coordinator and/or program committee member for several IEEE and ACM conferences. He is a Senior Member of the IEEE, a recipient of the 2006 Sheffield Distinguished Teaching Award and a recipient of the Best Paper Award from the 2013 Design Automation and Test in Europe (DATE'13) conference and the 2015 VLSI Test Symposium (VTS'15).

Host: Peter Beerel, beerel@usc.edu

Location: Hughes Aircraft Electrical Engineering Center (EEB) - 248

Audiences: Everyone Is Invited

Contact: Mayumi Thrasher