Handling Transient Errors in Logic Circuits

ELECTRICAL ENGINEERING - DISTINGUISHED LECTURER SERIESAbstract:Transient faults caused by external radiation or internal electrical noise are common in integrated circuits (ICs). They normally do no permanent physical damage, but they can produce complex logical errors that require probabilistic analysis techniques. The shrinking of ICs in accordance with Moore's Law is increasing susceptibility to errors of this type. Moreover, many of the nanotechnologies proposed to replace or supplement conventional ICs also have behavior, both normal and faulty, that is inherently probabilistic. In this talk, I will review transient faults and their impact. I will then discuss a method of modeling transient faults and a computational framework based on probabilistic transfer matrices for analyzing transient faults and errors in logic circuits.Bio: John P. Hayes is Professor of EECS at the University of Michigan, Ann Arbor where he holds the Claude E. Shannon Chair of Engineering Science. His teaching and research interests are in the areas of computer-aided design and testing; VLSI circuits; fault-tolerant systems; ad-hoc networks; and quantum computing. He received the B.E. degree from the National University of Ireland, and his M.S. and Ph.D. from the University of Illinois, all in electrical engineering. Prior to joining the University of Michigan, he was a faculty member at USC. Hayes was the founding director of Michigan’s Advanced Computer Architecture Laboratory (ACAL). He has authored numerous technical papers, several patents, and five books. He received the Michigan’s Distinguished Faculty Achievement Award in 1999 and the Humboldt Foundation’s Research Award in 2004. Hayes is a Fellow of both IEEE and ACM.HOSTS: Prof. Mel Breuer & Prof. Sandeep Gupta

Location: Ethel Percy Andrus Gerontology Center (GER) - ontology Auditorium

Audiences: Everyone Is Invited

Contact: Rosine Sarafian