Cache Architecture and Mapping for Packet Forwarding Applications

CENG SEMINAR SERIES"Cache Architecture and Mapping for Packet Forwarding Applications"Prof. Govind RamaswamySupercomputer Education and Research CentreIndian Institute of ScienceAbstract:Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. With the requirement to process packets at line rates high performance routers need to forward millions of packets every second. Even with an efficient lookup algorithm like the LC-trie, each packet needs up to 5 memory accesses. Earlier work shows that a single cache for the nodes of an LC-trie can reduce the number of external memory accesses. We propose a Heterogeneous Segmented Cache Architecture (HSCA) for packet forwarding application that exploits the significantly different locality characteristics of accesses to level-one and the lower-level nodes of an LC-trie. Further, we improve the hit rate of the cache for level-one nodes, which are accessed more than 80% of the time, by introducing a novel two-level mapping based cache placement scheme to reduce conflict misses.Performance results reveal that our base HSCA scheme reduces the number of misses incurred with a unified scheme by as much as 25%, leading to a 32% speedup in average memory access time. Two-level mapping further enhances the performance of the base HSCA by up to 13% leading to an overall improvement of up to 40% over the unified scheme.Bio:Govindarajan Ramaswamy received his B.Sc. degree in Mathematics from Madras University in 1981 and B.E. (Electronics and Communication) and Ph.D. (Computer Science) degrees from the Indian Institute of Science, Bangalore in 1984 and 1989 respectively. He has held post-doctoral and faculty positions in Canadian Universities between 1989-95. Since 1995 he has been a faculty in the Supercomputer Education and Research Centre and the Department of Computer Science and Automation, Indian Institute of Science, Bangalore, India. His research interests are in the areas of High Performance Computing, compilation techniques for instruction-level parallelism, and computer architecture.Host: Prof. Viktor Prasanna, Ext. 04483

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