VLSI Architecture Design for Algebraic Soft-decision

SPEAKER: Professor Xinmiao Zhang, Case Western Reserve UniversityAbstract: Reed-Solomon (RS) codes are among the most extensively used error-correcting codes in digital communication and storage systems. Recently, significant advancements have been made on algebraic soft-decision decoding (ASD) of RS codes. By incorporating the reliability information from the channel into an algebraic interpolation process, substantial coding gain can be achieved by these algorithms with a complexity that is polynomial with respect to the codeword length.ASD algorithms have two major steps: the interpolation and the factorization. In this talk, we focus on the factorization step and present complexity-reducing schemes and efficient VLSI implementation architectures for this step. The factorization can be implemented by an iterative algorithm, which mainly consists of root computations over finite fields and polynomial updating. Traditionally, root computations over finite fields are implemented by exhaustive search, which leads to very long latency. Based on the observation that the root-order in the first iteration is usually close to the degree of the polynomial and it only changes with very small probability in later iterations, we proposed prediction-based root computation schemes. Employing the proposed schemes, the roots can be found by simple direct computations if the prediction is correct. Since the prediction failure rates are very low, our schemes can bring significant speedup to the root computation. The involved polynomial updating is straightforward. However, a large number of polynomial coefficients need to be updated. In order to increase the speed, we employed a root-order-dependent parallel processing approach. Furthermore, a novel coefficient storage and transfer scheme is proposed to resolve the data dependency caused by the parallel processing and minimize the memory requirement. Applying our proposed schemes to the factorization of a (255, 239) RS decoding, a speedup of 228% can be achieved, while the area requirement has been reduced to less than 1/3.Bio: Xinmiao Zhang received the B.S. and M.S. degrees in Electrical Engineering from Tianjin University, Tianjin, China, in 1997 and 2000, respectively. She received her Ph.D. degree in Electrical Engineering from the University of Minnesota-Twin Cities, in 2005. Since then, she has been with Case Western Reserve University, where she is currently a Timothy E. and Allison L. Schroeder Assistant Professor in the Department of Electrical Engineering and Computer Science. Her research interests include VLSI architecture design for communications, cryptography, and digital signal processing.Ms. Zhang is the recipient of the Best Paper Award at ACM Great Lake Symposium on VLSI (GLSVLSI) 2004. She also won the First Prize in Student Paper Contest at the Asilomar Conference on Signals, Systems and Computers 2004. She is the co-editor of the book "Wireless Security and Cryptography: Specifications and Implementations" (CRC Press, 2007) and the guest editor for Springer MONET Journal Special Issue on "Next Generation Hardware Architectures for Secure Mobile Computing". She has served on technical program committees of GLSVLSI and the reviewer committees of IEEE International Symposium on Circuits and Systems (ISCAS).Host: Prof. Keith Chugg, chugg@usc.edu

Location: Hughes Aircraft Electrical Engineering Center (EEB) - 248

Audiences: Everyone Is Invited

Contact: Mayumi Thrasher