Pseudospintronics for Ultra-Low Power Logic Devices

Matthew J. GilbertMicroelectronics Research Center, University of Texas at AustinAbstract
As the march towards ever smaller silicon devices continues unabated, we are rapidly approaching size scales where the bulk silicon transistor can no longer deliver sufficient device performance. The main problem with using charge based devices for next generation logic devices is that their performance has basic and fundamental physical limitations. While new device designs may extend the life of CMOS for several years, concerns about the power dissipation in these future generation CMOS devices has fueled the search for new computational state variables and the tools with which to evaluate these new devices.
In this talk, we will discuss the possibility of exploiting the exotic phenomena of strongly interacting systems to produce a completely new generation of logic devices based on collective behavior. In particular, we will discuss the device and transport properties of "pseudospintronic" systems. Pseudospintronics is a variant of spintronics where we represent the layer degree of freedom in a bilayer system (e.g. coupled quantum wells) as a spin. When the layers are separated by a small distance (~1 - 10 nm), the quasiparticles in each of the layers interact with one another. This interaction can greatly enhance the interlayer transport. We will discuss the application of this interaction-enhanced interlayer transport in III-V electron doped bilayers to elucidate the cause of the interlayer currents and the decay of the enhancement with increasing bias known as the "pseudospin torque effect". We also discuss a silicon based pseudospin system consisting of one electron doped layer and one hole doped layer. In this system we find reduced interlayer currents which arise from the discrepancy in dispersion relations between the two layers. Nevertheless, at elevated temperatures, both the III-V and silicon systems lose their interaction based enhancements.
We conclude our discussion by examining separately contacted, non-bonded graphene bilayer systems. These are devices that can have output characteristics very similar to a MOSFET, but while requiring much less switching energy. Furthermore, calculations show that the performance will not degrade at room temperature. Efforts are underway at Stanford University to experimentally realize graphene bilayer nanoswitches. Biography: Matthew Gilbert received the B.S. (Honors), M.S. and Ph.D. degrees from Arizona State University in 2000, 2003, and 2005 respectively all in electrical engineering. His Ph.D. research focused on novel systems for quantum computing and electron-phonon interactions in tri-gate nanowire transistors. He is currently the assistant director of the SouthWest Academy of Nanoelectronics (SWAN) and a post-doctoral fellow at the University of Texas at Austin. His research focuses on emergent semiconductor nanodevice technology which exploits computational state variables beyond that of charge (e.g. spin and phase) and their application to form beyond CMOS architectures. He has published over 40 conference and journal papers in the areas of spintronics, semiconductor nanowire MOS devices, graphene, computational algorithms for efficient transport calculation and correlated many-body systems and theory. Date: Tuesday, April 8, 2008
Place: OHE 120
Time: 2:00 PM – 3:00 PM

Location: Olin Hall of Engineering (OHE) - 120

Audiences: Everyone Is Invited

Contact: Ericka Lieberknecht