Seminar: Robust Heterogeneous Systems in Emerging Technologies: A TFT-CMOS 3D System for Testable/Re

Jing Li
PhD Candidate, Purdue UniversityAbstract:
Moore's law has provided a metronome for semiconductor technology over the past four decades. However, when CMOS feature size and interconnect dimensions approach the fundamental limit, aggressive scaling no longer plays an exclusive role in improving performance. An emphasis on emerging technologies and computational paradigms has been placed. To meet the fast growing demand for system functionality, heterogeneous system that utilizes and optimizes the best of different technologies is becoming one of the most promising solutions for future complex system design. In heterogeneous system, Si CMOS will continue to play a major role for high performance computation while the other technologies can add special functions that are either difficult, expensive, or even not achievable with standard silicon CMOS. However, designing such ultra-complex systems with various technologies also poses a set of new challenges (in terms of design, test, fabrication and integration). Those challenges will ultimately lead to a paradigm shift from traditional system design (assembling separate functional blocks) to a completely new paradigm (designing them in a holistic way). In the new paradigm, device engineering and system design should not be considered separately. On the contrary, an optimal system design should consider the strong interaction between technology/device and circuit/system. To demonstrate the feasibility of the proposed system design concept, in this talk, I will focus on one interesting technology - flexible electronics (Thin Film Transistors). This technology has been widely used in LCD applications due to its low cost and manufacturability on flexible substrates (polymer, flexible glass, etc.). However, further application of TFT is limited by its performance, reliability, and inherent material induced process variations (i.e., grain boundary). To cope with these challenges, both modeling and design techniques have been developed. In particular, I will discuss device optimization, statistical simulation methodology for estimation of process variations, followed by an efficient circuit-level variability compensation technique. Optimized LTPS TFTs with higher current drivability and less variability would make them as an effective add-on (as auxiliary functions) to Si CMOS, opening up a plethora of new and interesting applications. At architecture level, I will focus on one such application â€" low-cost and robust Si-TFT heterogeneous system design with on-line/off-line built-in-test circuits, implemented in LTPS-TFTs, to test the underlying silicon CMOS die. Such a system significantly reduces the test cost and improves the controllability and observability of the underlying Si CMOS die for ensuring highly reliable and testable operations. Bio:
Jing (Vicky) Li is a PH.D. candidate from the Electrical and Computer Engineering department at Purdue University, West Lafayette, IN. She received the B.S. degree from Electrical Engineering at Shanghai Jiao Tong University, Shanghai, China, in 2004. In 2008 summer, she worked as a research intern at IBM Semiconductor Research and Development Center (SRDC), Fishkill, NY. She has received the IBM PH.D. fellowship award in 2008, the Dean's and Semester Honors for outstanding scholastics performance (Graduate School Fellowship) from Purdue University in 2007, the Meissner Fellowship from Purdue University in 2004 and Geare scholarship from Purdue and Shanghai Jiao Tong University in her undergraduate senior year (2003). She was also the recipient of the 2005~2006 Magoon's award for excellence in teaching from Purdue University. Her primary research focus encompasses the development of innovative techniques for green heterogeneous systems using emerging technologies (flexible electronics, spintronics, etc.) integrated with Si CMOS. This research has a strong emphasis on interdisciplinary field between device physics, material science and VLSI circuit/system design, bridging the technical gap between fundamental devices physics and high-level system design/optimization.

Location: Hughes Aircraft Electrical Engineering Center (EEB) - -248

Audiences: Everyone Is Invited

Contact: Estela Lopez