Nanoelectronics: Technology Assessment and Projection at the Device, Circuit and System level

Presented by Lan WeiAbstract:
Nowadays, physical gate length can no longer be effectively scaled down and traditional boosters (e.g., strain, high-k/metal gate) are exhibiting diminishing returns on performance improvement. Continued progress in nanoelectronics necessitates a holistic view across the boundaries of device, circuit and system domains. The best devices are those that are optimized for the circuits and systems of the target application. Device design and engineering must aim at improvements at the circuit and system levels.
In this talk, the design space is explored for future Si CMOS technology and for carbon nanotube field effect transistors, a promising technology in the post-Si era. Compact models for transport properties and capacitive components of different device structures have been developed to facilitate circuit-level analysis and system-level optimization. Possible ways of extending the technology roadmap are proposed. We propose scenarios of selective device structure scaling that will enable Si CMOS technology scaling for several generations beyond the currently perceived limits. Beyond Si CMOS scaling, carbon nanotube field effect transistors (CNFETs) are optimized and projected to achieve 5x chip-level speed up over PDSOI at 11 nm technology node for a high-performance four-core processor with 1.5M logic gates. Biography:
Lan Wei received her B. S. in Microelectronics and Economics from Peking University in 2005 and M. S. in Electrical Engineering from Stanford University in 2007. She is currently a Ph. D. candidate in Electrical Engineering at Stanford University, under the supervision of Prof. H. –S. Philip Wong in the Stanford Nanoelectronics Group. Her Ph.D. research focuses on technology scaling with a holistic view across the traditional boundaries of device, circuit, and system domains, as well as integrated bio-systems and biomedical devices. She worked as a research intern at Intel (2006), IBM Research (2007), STMicroelectronics (2008), and Grenoble Institute of Technology (2008). She has contributed to the PIDS (Process Integration, Devices, and Structures) Chapter of ITRS (International Technology Roadmap for Semiconductors) 2009 Edition. Lan Wei was a recipient of a number of awards, including Stanford Graduate Fellowship (2005-2009).

Location: Hughes Aircraft Electrical Engineering Center (EEB) - 248

Audiences: Everyone Is Invited

Contact: Hazel Xavier