SUNMONTUEWEDTHUFRISAT
Events for the 5th week of March
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ECE Seminar Announcement: Accelerating Chip-Building Design Cycles for Future Generations of Computing
Mon, Mar 28, 2022 @ 10:00 AM - 11:00 AM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Speaker: Dr. Christopher Torng, Postdoctoral Researcher, Stanford University
Talk Title: Accelerating Chip-Building Design Cycles for Future Generations of Computing
Abstract: The chip building industry is a major cornerstone of the global economy. As a result, addressing the causes behind a multi-year global chip shortage is important for both near and long term futures. Unfortunately, one major challenge is that it is difficult to produce high-quality designs quickly and at low cost using traditional hardware design flows. This means that the industry wastes valuable fabrication slots learning painful design lessons rather than meeting economic demands.
My research focuses on building new architectures, systems, and design tools to accelerate chip building design cycles for future generations of computing systems. To support this goal, my research spans across the computing stack, ranging from applications, compilers, architectures, and down to chip implementation. In this talk, I will first present a set of vertically integrated techniques (compiler, architecture, and VLSI) that significantly reduces the design effort for extremely fine-grain power control in spatial architectures. Next, I will introduce my work on a new generation of open and agile hardware flow tools that leverage modern programming language features to increase code reuse in physical design. Finally, I will discuss recent work on Amber SoC, a coarse-grained reconfigurable array designed with an end-to-end agile accelerator-compiler co-designed flow. I will conclude with my future directions in supporting chip building for the next generation of computing.
Biography: Christopher Torng is a postdoctoral researcher at Stanford University. He received his Ph.D. degree, M.S. degree, and B.S degree (2019, 2016, 2012) in Electrical and Computer Engineering from Cornell University. His projects target the development of architectures and tools to accelerate building chips and complex hardware systems. His tools have achieved use across multiple universities to support over ten academic tapeouts in technologies ranging from 180nm to 16nm. His activities have resulted in a selection as a Rising Star in Computer Architecture (2018) by Georgia Tech and an IEEE MICRO Top Pick from Hot Chips (2018).
Host: Dr. Peter Beerel, pabeerel@usc.edu
Webcast: https://usc.zoom.us/j/99531222900?pwd=S1VDR2pRU2lyZ2hORmtObE1PcFh6Zz09Location: Hughes Aircraft Electrical Engineering Center (EEB) - 248
WebCast Link: https://usc.zoom.us/j/99531222900?pwd=S1VDR2pRU2lyZ2hORmtObE1PcFh6Zz09
Audiences: Everyone Is Invited
Contact: Mayumi Thrasher
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Center of Autonomy and AI, Center for Cyber-Physical Systems and the Internet of Things, and Ming Hsieh Institute Seminar Series
Wed, Mar 30, 2022 @ 11:00 AM - 12:00 PM
Ming Hsieh Department of Electrical and Computer Engineering
Conferences, Lectures, & Seminars
Speaker: Nir Piterman, Department of Computer Science and Engineering, University of Gothenburg, Sweden
Talk Title: Synthesis From Temporal Specifications
Series: Center for Cyber-Physical Systems and Internet of Things
Abstract: In this talk I will present the GR[1] approach to synthesis, the automatic production of designs from their temporal logic specifications. We are interested in reactive systems, systems that continuously interact with other programs, users, or their environment and specifications in linear temporal logic. Classical solutions to synthesis use either two player games or tree automata. I will give a short introduction to the technique of using two player games for synthesis.
The classical solution to synthesis requires the usage of deterministic automata. This solution is 2EXPTIME-complete, is quite complicated, and does not work well in practice. I will present a syntactic approach that restricts the kind of properties users are allowed to write. It turns out that this approach is general enough and can be extended to cover many properties written in practice.
Time permitting, I will present results that support the usage of synthesis in model-driven development and robot control.
Biography: Nir Piterman is a professor of computer science at the University of Gothenburg in Sweden. Before that he was an associate professor at the University of Leicester, held postdoctoral research positions at Imperial College London and the Ecole Polytechnique Federal de Lausanne, and completed his PhD at the Weizmann Institute of Science. His research interests include formal verification and automata theory. Particularly, he has worked on model checking, temporal logic, reactive synthesis, and game solving. His current research is funded by the European Research Council (ERC), the Swedish Research Council (VR), and the Wallenberg Autonomous Systems Program (WASP(. He is currently the editor in chief of the journal Formal Methods in System Design.
Host: Pierluigi Nuzzo, nuzzo@usc.edu
Location: Online
Audiences: Everyone Is Invited
Contact: Talyia White